How to modify the Verilog code? :     module make_counter(h, clk, P);
        input wire h;
        input wire clk;
        output wire P;
        reg r=1'b1;
        reg[9:0] n=0;
    
        always @(negedge clk)
              always @(posedge h)
              begin 
                  n=0;
              end
              
              begin
              if(n<600)
                    n=n+1'b1;
                    
              if(n==106)
                    r<=1'b0;
              else if(n==517)
                    r<=1'b1;
              else 
                    ;
              end
        assign P=r;
    endmodule

Error (10170): Verilog HDL syntax error at main.v(115) near text "always";  expecting ";"
Error (10170): Verilog HDL syntax error at main.v(119) near text "begin";  expecting "endmodule"

