i keep getting this syntax error in verilog? : module mux ( in1 , in2 , sel , out1 );

input wire [31:0] in1 , in2;

output reg [31:0] out;

input wire sel;

case (sel)

0 : begin out1 <= in1 ; end 
 
default : begin out1 <= in2 ; end

endcase 

endmodule


the error is:
** Error: (vlog-13069) C:/Modeltech_pe_edu_10.4a/examples/mux.v(9): near "<=": syntax error, unexpected <=.

** Error: C:/Modeltech_pe_edu_10.4a/examples/mux.v(9): (vlog-13205) Syntax error found in the scope following 'out1'. Is there a missing '::'?