Trouble Converting VHDL to Verilog : I am trying to convert the vhdl code below to verilog, and it is not working properly. I have already done most of it, but I think I may have converted the VHDL keyword others incorrectly. Could anyone please help?

## VHDL Code ##
    entity debounce is
    Port ( clk : in  STD_LOGIC;
           i : in  STD_LOGIC;
           o : out  STD_LOGIC);
    end debounce;

    architecture Behavioral of debounce is
        signal c : unsigned(23 downto 0);
    begin
       process(clk)
       begin
          if rising_edge(clk) then
             if i = '1' then
                if c = x"FFFFFF" then
                   o <= '1';
                else
                   o <= '0';
                end if;
                c <= c+1;
             else
                c <= (others => '0');   --LINE IN QUESTION
                o <= '0';
             end if;
          end if;
      end process;
   end Behavioral;
## My Verilog Code ##

    module debounce(input clk, input i, output o); 
        reg unsigned [23:0] c;
        reg out_temp;
        always @(posedge clk)begin
            if(i == 1)begin
                if(c==24'hFFFFFF)begin
                    out_temp = 1'b1;           
                end
                else begin
                    out_temp = 1'b0;
                end
                c = c+1'b1;
            end
            else begin
                c = 1'b0;          // LINE IN QUESTION    
                out_temp = 1'b0;
            end
        end
        assign o = out_temp;
    endmodule