Verilog: if else to Casex conversion : <pre><code>reg A, B, C, D, E, F, G, H;
always@(*)
if (A) H = F &amp; G;
else if (B) H = F | G;
else if (C) H = F ^ G;
else H = D &amp; E;
</code></pre>

<p>I have to replace these statements with a casex statement. Can someone help me with the code</p>

<p>My code is this which is wrong ....</p>

<pre><code>reg A, B, C, D, E, F, G, H;
always@(*)
begin
casex(A or B or C or D or E or F or G or H)
A: H= F &amp; G;
B: H = F | G;
C: H = F ^ G;
default: H = D &amp; E;
endcase
</code></pre>
