Verilog - re-using register valueon Edge vent : ----------
Consider the following code:

       Module Test  (B, A CLK)
    
    Input A; CLK
    Output B
    
    Reg RA;
    
    Always @(Posedge CLK)
    
    Begin
    
    RA=A;
    B=RA;
    
    End
    EndModule

Would that work properly to move the input to the register and then to the output on every positive edge? Can it be created with circuits?
