CpuInfoList *qmp_query_cpus(Error **errp)

{

    MachineState *ms = MACHINE(qdev_get_machine());

    MachineClass *mc = MACHINE_GET_CLASS(ms);

    CpuInfoList *head = NULL, *cur_item = NULL;

    CPUState *cpu;

    CPU_FOREACH(cpu) {

        CpuInfoList *info;

#if defined(TARGET_I386)

        X86CPU *x86_cpu = X86_CPU(cpu);

        CPUX86State *env = &x86_cpu->env;

#elif defined(TARGET_PPC)

        PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);

        CPUPPCState *env = &ppc_cpu->env;

#elif defined(TARGET_SPARC)

        SPARCCPU *sparc_cpu = SPARC_CPU(cpu);

        CPUSPARCState *env = &sparc_cpu->env;

#elif defined(TARGET_MIPS)

        MIPSCPU *mips_cpu = MIPS_CPU(cpu);

        CPUMIPSState *env = &mips_cpu->env;

#elif defined(TARGET_TRICORE)

        TriCoreCPU *tricore_cpu = TRICORE_CPU(cpu);

        CPUTriCoreState *env = &tricore_cpu->env;

#endif

        cpu_synchronize_state(cpu);

        info = g_malloc0(sizeof(*info));

        info->value = g_malloc0(sizeof(*info->value));

        info->value->CPU = cpu->cpu_index;

        info->value->current = (cpu == first_cpu);

        info->value->halted = cpu->halted;

        info->value->qom_path = object_get_canonical_path(OBJECT(cpu));

        info->value->thread_id = cpu->thread_id;

#if defined(TARGET_I386)

        info->value->arch = CPU_INFO_ARCH_X86;

        info->value->u.x86.pc = env->eip + env->segs[R_CS].base;

#elif defined(TARGET_PPC)

        info->value->arch = CPU_INFO_ARCH_PPC;

        info->value->u.ppc.nip = env->nip;

#elif defined(TARGET_SPARC)

        info->value->arch = CPU_INFO_ARCH_SPARC;

        info->value->u.q_sparc.pc = env->pc;

        info->value->u.q_sparc.npc = env->npc;

#elif defined(TARGET_MIPS)

        info->value->arch = CPU_INFO_ARCH_MIPS;

        info->value->u.q_mips.PC = env->active_tc.PC;

#elif defined(TARGET_TRICORE)

        info->value->arch = CPU_INFO_ARCH_TRICORE;

        info->value->u.tricore.PC = env->PC;

#else

        info->value->arch = CPU_INFO_ARCH_OTHER;

#endif

        /* XXX: waiting for the qapi to support GSList */

        if (!cur_item) {

            head = cur_item = info;

        } else {

            cur_item->next = info;

            cur_item = info;

    return head;


static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,

                                     ppc_slb_t *slb, target_ulong eaddr,

                                     ppc_hash_pte64_t *pte)

{

    CPUPPCState *env = &cpu->env;

    hwaddr pte_offset;

    hwaddr hash;

    uint64_t vsid, epnmask, epn, ptem;

    /* The SLB store path should prevent any bad page size encodings

     * getting in there, so: */

    assert(slb->sps);

    epnmask = ~((1ULL << slb->sps->page_shift) - 1);

    if (slb->vsid & SLB_VSID_B) {

        /* 1TB segment */

        vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;

        epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;

        hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift);

    } else {

        /* 256M segment */

        vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;

        epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;

        hash = vsid ^ (epn >> slb->sps->page_shift);

    }

    ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);

    /* Page address translation */

    qemu_log_mask(CPU_LOG_MMU,

            "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx

            " hash " TARGET_FMT_plx "\n",

            env->htab_base, env->htab_mask, hash);

    /* Primary PTEG lookup */

    qemu_log_mask(CPU_LOG_MMU,

            "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx

            " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx

            " hash=" TARGET_FMT_plx "\n",

            env->htab_base, env->htab_mask, vsid, ptem,  hash);

    pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, 0, ptem, pte);

    if (pte_offset == -1) {

        /* Secondary PTEG lookup */

        qemu_log_mask(CPU_LOG_MMU,

                "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx

                " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx

                " hash=" TARGET_FMT_plx "\n", env->htab_base,

                env->htab_mask, vsid, ptem, ~hash);

        pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, 1, ptem, pte);

    }

    return pte_offset;

}


static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)

{

    int l1, l2;

    l1 = gen_new_label();

    l2 = gen_new_label();

#if defined(TARGET_PPC64)

    if (ctx->sf_mode) {

        tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);

    } else {

        TCGv t0 = tcg_temp_new(TCG_TYPE_TL);

	tcg_gen_ext32s_tl(t0, arg1);

        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);

    }

#else

        tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);

#endif

    tcg_gen_neg_tl(ret, arg1);

    if (ov_check) {

        tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

    }

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_mov_tl(ret, arg1);

    if (ov_check) {

        tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));

    }

    gen_set_label(l2);

    if (unlikely(Rc(ctx->opcode) != 0))

        gen_set_Rc0(ctx, ret);

}


static int tx_consume(Rocker *r, DescInfo *info)

{

    PCIDevice *dev = PCI_DEVICE(r);

    char *buf = desc_get_buf(info, true);

    RockerTlv *tlv_frag;

    RockerTlv *tlvs[ROCKER_TLV_TX_MAX + 1];

    struct iovec iov[ROCKER_TX_FRAGS_MAX] = { { 0, }, };

    uint32_t pport;

    uint32_t port;

    uint16_t tx_offload = ROCKER_TX_OFFLOAD_NONE;

    uint16_t tx_l3_csum_off = 0;

    uint16_t tx_tso_mss = 0;

    uint16_t tx_tso_hdr_len = 0;

    int iovcnt = 0;

    int err = ROCKER_OK;

    int rem;

    int i;

    if (!buf) {

        return -ROCKER_ENXIO;

    }

    rocker_tlv_parse(tlvs, ROCKER_TLV_TX_MAX, buf, desc_tlv_size(info));

    if (!tlvs[ROCKER_TLV_TX_FRAGS]) {

        return -ROCKER_EINVAL;

    }

    pport = rocker_get_pport_by_tx_ring(r, desc_get_ring(info));

    if (!fp_port_from_pport(pport, &port)) {

        return -ROCKER_EINVAL;

    }

    if (tlvs[ROCKER_TLV_TX_OFFLOAD]) {

        tx_offload = rocker_tlv_get_u8(tlvs[ROCKER_TLV_TX_OFFLOAD]);

    }

    switch (tx_offload) {

    case ROCKER_TX_OFFLOAD_L3_CSUM:

        if (!tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {

            return -ROCKER_EINVAL;

        }

        break;

    case ROCKER_TX_OFFLOAD_TSO:

        if (!tlvs[ROCKER_TLV_TX_TSO_MSS] ||

            !tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {

            return -ROCKER_EINVAL;

        }

        break;

    }

    if (tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]) {

        tx_l3_csum_off = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_L3_CSUM_OFF]);

    }

    if (tlvs[ROCKER_TLV_TX_TSO_MSS]) {

        tx_tso_mss = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_MSS]);

    }

    if (tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]) {

        tx_tso_hdr_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_TSO_HDR_LEN]);

    }

    rocker_tlv_for_each_nested(tlv_frag, tlvs[ROCKER_TLV_TX_FRAGS], rem) {

        hwaddr frag_addr;

        uint16_t frag_len;

        if (rocker_tlv_type(tlv_frag) != ROCKER_TLV_TX_FRAG) {

            err = -ROCKER_EINVAL;

            goto err_bad_attr;

        }

        rocker_tlv_parse_nested(tlvs, ROCKER_TLV_TX_FRAG_ATTR_MAX, tlv_frag);

        if (!tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR] ||

            !tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]) {

            err = -ROCKER_EINVAL;

            goto err_bad_attr;

        }

        frag_addr = rocker_tlv_get_le64(tlvs[ROCKER_TLV_TX_FRAG_ATTR_ADDR]);

        frag_len = rocker_tlv_get_le16(tlvs[ROCKER_TLV_TX_FRAG_ATTR_LEN]);

        iov[iovcnt].iov_len = frag_len;

        iov[iovcnt].iov_base = g_malloc(frag_len);

        if (!iov[iovcnt].iov_base) {

            err = -ROCKER_ENOMEM;

            goto err_no_mem;

        }

        if (pci_dma_read(dev, frag_addr, iov[iovcnt].iov_base,

                     iov[iovcnt].iov_len)) {

            err = -ROCKER_ENXIO;

            goto err_bad_io;

        }

        if (++iovcnt > ROCKER_TX_FRAGS_MAX) {

            goto err_too_many_frags;

        }

    }

    if (iovcnt) {

        /* XXX perform Tx offloads */

        /* XXX   silence compiler for now */

        tx_l3_csum_off += tx_tso_mss = tx_tso_hdr_len = 0;

    }

    err = fp_port_eg(r->fp_port[port], iov, iovcnt);

err_too_many_frags:

err_bad_io:

err_no_mem:

err_bad_attr:

    for (i = 0; i < ROCKER_TX_FRAGS_MAX; i++) {

        g_free(iov[i].iov_base);

    }

    return err;

}


static void gen_neon_dup_low16(TCGv var)

{

    TCGv tmp = new_tmp();

    tcg_gen_ext16u_i32(var, var);

    tcg_gen_shli_i32(tmp, var, 16);

    tcg_gen_or_i32(var, var, tmp);

    dead_tmp(tmp);

}


static void audio_print_settings (audsettings_t *as)

{

    dolog ("frequency=%d nchannels=%d fmt=", as->freq, as->nchannels);

    switch (as->fmt) {

    case AUD_FMT_S8:

        AUD_log (NULL, "S8");

        break;

    case AUD_FMT_U8:

        AUD_log (NULL, "U8");

        break;

    case AUD_FMT_S16:

        AUD_log (NULL, "S16");

        break;

    case AUD_FMT_U16:

        AUD_log (NULL, "U16");

        break;

    case AUD_FMT_S32:

        AUD_log (NULL, "S32");

        break;

    case AUD_FMT_U32:

        AUD_log (NULL, "U32");

        break;

    default:

        AUD_log (NULL, "invalid(%d)", as->fmt);

        break;

    }

    AUD_log (NULL, " endianness=");

    switch (as->endianness) {

    case 0:

        AUD_log (NULL, "little");

        break;

    case 1:

        AUD_log (NULL, "big");

        break;

    default:

        AUD_log (NULL, "invalid");

        break;

    }

    AUD_log (NULL, "\n");

}


static void vnc_refresh(void *opaque)

{

    VncDisplay *vd = opaque;

    VncState *vs, *vn;

    int has_dirty, rects = 0;

    vga_hw_update();

    if (vnc_trylock_display(vd)) {

        vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;

        qemu_mod_timer(vd->timer, qemu_get_clock(rt_clock) +

                       vd->timer_interval);

        return;

    }

    has_dirty = vnc_refresh_server_surface(vd);

    vnc_unlock_display(vd);

    QTAILQ_FOREACH_SAFE(vs, &vd->clients, next, vn) {

        rects += vnc_update_client(vs, has_dirty);

        /* vs might be free()ed here */

    }

    /* vd->timer could be NULL now if the last client disconnected,

     * in this case don't update the timer */

    if (vd->timer == NULL)

        return;

    if (has_dirty && rects) {

        vd->timer_interval /= 2;

        if (vd->timer_interval < VNC_REFRESH_INTERVAL_BASE)

            vd->timer_interval = VNC_REFRESH_INTERVAL_BASE;

    } else {

        vd->timer_interval += VNC_REFRESH_INTERVAL_INC;

        if (vd->timer_interval > VNC_REFRESH_INTERVAL_MAX)

            vd->timer_interval = VNC_REFRESH_INTERVAL_MAX;

    }

    qemu_mod_timer(vd->timer, qemu_get_clock(rt_clock) + vd->timer_interval);

}


static void set_pointer(Object *obj, Visitor *v, Property *prop,

                        int (*parse)(DeviceState *dev, const char *str, void **ptr),

                        const char *name, Error **errp)

{

    DeviceState *dev = DEVICE(obj);

    Error *local_err = NULL;

    void **ptr = qdev_get_prop_ptr(dev, prop);

    char *str;

    int ret;

    if (dev->state != DEV_STATE_CREATED) {

        error_set(errp, QERR_PERMISSION_DENIED);

        return;

    }

    visit_type_str(v, &str, name, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }

    if (!*str) {

        g_free(str);

        *ptr = NULL;

        return;

    }

    ret = parse(dev, str, ptr);

    error_set_from_qdev_prop_error(errp, ret, dev, prop, str);

    g_free(str);

}


static int scsi_hd_initfn(SCSIDevice *dev)

{

    SCSIDiskState *s = DO_UPCAST(SCSIDiskState, qdev, dev);

    s->qdev.blocksize = s->qdev.conf.logical_block_size;

    s->qdev.type = TYPE_DISK;

    if (!s->product) {

        s->product = g_strdup("QEMU HARDDISK");

    }

    return scsi_initfn(&s->qdev);

}


static int local_parse_opts(QemuOpts *opts, struct FsDriverEntry *fse)

{

    const char *sec_model = qemu_opt_get(opts, "security_model");

    const char *path = qemu_opt_get(opts, "path");

    if (!sec_model) {

        fprintf(stderr, "security model not specified, "

                "local fs needs security model\nvalid options are:"

                "\tsecurity_model=[passthrough|mapped|none]\n");

        return -1;

    }

    if (!strcmp(sec_model, "passthrough")) {

        fse->export_flags |= V9FS_SM_PASSTHROUGH;

    } else if (!strcmp(sec_model, "mapped")) {

        fse->export_flags |= V9FS_SM_MAPPED;

    } else if (!strcmp(sec_model, "none")) {

        fse->export_flags |= V9FS_SM_NONE;

    } else {

        fprintf(stderr, "Invalid security model %s specified, valid options are"

                "\n\t [passthrough|mapped|none]\n", sec_model);

        return -1;

    }

    if (!path) {

        fprintf(stderr, "fsdev: No path specified.\n");

        return -1;

    }

    fse->path = g_strdup(path);

    return 0;

}


static void spr_write_dbatl_h (void *opaque, int sprn)

{

    DisasContext *ctx = opaque;

    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);

    RET_STOP(ctx);

}


static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,

                          TCGv r_cond, TCGv r_reg)

{

    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));

    target_ulong target = dc->pc + offset;

    flush_cond(dc, r_cond);

    gen_cond_reg(r_cond, cond, r_reg);

    if (a) {

        gen_branch_a(dc, target, dc->npc, r_cond);

        dc->is_br = 1;

    } else {

        dc->pc = dc->npc;

        dc->jump_pc[0] = target;

        dc->jump_pc[1] = dc->npc + 4;

        dc->npc = JUMP_PC;

    }

}