void framebuffer_update_display(

    DisplaySurface *ds,

    MemoryRegion *address_space,

    hwaddr base,

    int cols, /* Width in pixels.  */

    int rows, /* Height in pixels.  */

    int src_width, /* Length of source line, in bytes.  */

    int dest_row_pitch, /* Bytes between adjacent horizontal output pixels.  */

    int dest_col_pitch, /* Bytes between adjacent vertical output pixels.  */

    int invalidate, /* nonzero to redraw the whole image.  */

    drawfn fn,

    void *opaque,

    int *first_row, /* Input and output.  */

    int *last_row /* Output only */)

{

    hwaddr src_len;

    uint8_t *dest;

    uint8_t *src;

    uint8_t *src_base;

    int first, last = 0;

    int dirty;

    int i;

    ram_addr_t addr;

    MemoryRegionSection mem_section;

    MemoryRegion *mem;

    i = *first_row;

    *first_row = -1;

    src_len = src_width * rows;

    mem_section = memory_region_find(address_space, base, src_len);

    if (int128_get64(mem_section.size) != src_len ||

            !memory_region_is_ram(mem_section.mr)) {

        return;

    }

    mem = mem_section.mr;

    assert(mem);

    assert(mem_section.offset_within_address_space == base);

    memory_region_sync_dirty_bitmap(mem);

    src_base = cpu_physical_memory_map(base, &src_len, 0);

    /* If we can't map the framebuffer then bail.  We could try harder,

       but it's not really worth it as dirty flag tracking will probably

       already have failed above.  */

    if (!src_base)

        return;

    if (src_len != src_width * rows) {

        cpu_physical_memory_unmap(src_base, src_len, 0, 0);

        return;

    }

    src = src_base;

    dest = surface_data(ds);

    if (dest_col_pitch < 0)

        dest -= dest_col_pitch * (cols - 1);

    if (dest_row_pitch < 0) {

        dest -= dest_row_pitch * (rows - 1);

    }

    first = -1;

    addr = mem_section.offset_within_region;

    addr += i * src_width;

    src += i * src_width;

    dest += i * dest_row_pitch;

    for (; i < rows; i++) {

        dirty = memory_region_get_dirty(mem, addr, src_width,

                                             DIRTY_MEMORY_VGA);

        if (dirty || invalidate) {

            fn(opaque, dest, src, cols, dest_col_pitch);

            if (first == -1)

                first = i;

            last = i;

        }

        addr += src_width;

        src += src_width;

        dest += dest_row_pitch;

    }

    cpu_physical_memory_unmap(src_base, src_len, 0, 0);

    if (first < 0) {

        return;

    }

    memory_region_reset_dirty(mem, mem_section.offset_within_region, src_len,

                              DIRTY_MEMORY_VGA);

    *first_row = first;

    *last_row = last;

}


void tcg_region_reset_all(void)

{

    unsigned int i;

    qemu_mutex_lock(&region.lock);

    region.current = 0;

    region.agg_size_full = 0;

    for (i = 0; i < n_tcg_ctxs; i++) {

        bool err = tcg_region_initial_alloc__locked(tcg_ctxs[i]);

        g_assert(!err);

    }

    qemu_mutex_unlock(&region.lock);

}


static int parse_args(int argc, char **argv)

{

    const char *r;

    int optind;

    struct qemu_argument *arginfo;

    for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {

        if (arginfo->env == NULL) {

            continue;

        }

        r = getenv(arginfo->env);

        if (r != NULL) {

            arginfo->handle_opt(r);

        }

    }

    optind = 1;

    for (;;) {

        if (optind >= argc) {

            break;

        }

        r = argv[optind];

        if (r[0] != '-') {

            break;

        }

        optind++;

        r++;

        if (!strcmp(r, "-")) {

            break;

        }

        for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {

            if (!strcmp(r, arginfo->argv)) {

                if (optind >= argc) {

                    usage();

                }

                arginfo->handle_opt(argv[optind]);

                if (arginfo->has_arg) {

                    optind++;

                }

                break;

            }

        }

        /* no option matched the current argv */

        if (arginfo->handle_opt == NULL) {

            usage();

        }

    }

    if (optind >= argc) {

        usage();

    }

    filename = argv[optind];

    exec_path = argv[optind];

    return optind;

}


void cpu_loop(CPUOpenRISCState *env)

{

    CPUState *cs = CPU(openrisc_env_get_cpu(env));

    int trapnr, gdbsig;

    for (;;) {

        cpu_exec_start(cs);

        trapnr = cpu_openrisc_exec(cs);

        cpu_exec_end(cs);

        gdbsig = 0;

        switch (trapnr) {

        case EXCP_RESET:

            qemu_log("\nReset request, exit, pc is %#x\n", env->pc);

            exit(EXIT_FAILURE);

            break;

        case EXCP_BUSERR:

            qemu_log("\nBus error, exit, pc is %#x\n", env->pc);

            gdbsig = TARGET_SIGBUS;

            break;

        case EXCP_DPF:

        case EXCP_IPF:

            cpu_dump_state(cs, stderr, fprintf, 0);

            gdbsig = TARGET_SIGSEGV;

            break;

        case EXCP_TICK:

            qemu_log("\nTick time interrupt pc is %#x\n", env->pc);

            break;

        case EXCP_ALIGN:

            qemu_log("\nAlignment pc is %#x\n", env->pc);

            gdbsig = TARGET_SIGBUS;

            break;

        case EXCP_ILLEGAL:

            qemu_log("\nIllegal instructionpc is %#x\n", env->pc);

            gdbsig = TARGET_SIGILL;

            break;

        case EXCP_INT:

            qemu_log("\nExternal interruptpc is %#x\n", env->pc);

            break;

        case EXCP_DTLBMISS:

        case EXCP_ITLBMISS:

            qemu_log("\nTLB miss\n");

            break;

        case EXCP_RANGE:

            qemu_log("\nRange\n");

            gdbsig = TARGET_SIGSEGV;

            break;

        case EXCP_SYSCALL:

            env->pc += 4;   /* 0xc00; */

            env->gpr[11] = do_syscall(env,

                                      env->gpr[11], /* return value       */

                                      env->gpr[3],  /* r3 - r7 are params */

                                      env->gpr[4],

                                      env->gpr[5],

                                      env->gpr[6],

                                      env->gpr[7],

                                      env->gpr[8], 0, 0);

            break;

        case EXCP_FPE:

            qemu_log("\nFloating point error\n");

            break;

        case EXCP_TRAP:

            qemu_log("\nTrap\n");

            gdbsig = TARGET_SIGTRAP;

            break;

        case EXCP_NR:

            qemu_log("\nNR\n");

            break;

        default:

            qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",

                     trapnr);

            cpu_dump_state(cs, stderr, fprintf, 0);

            gdbsig = TARGET_SIGILL;

            break;

        }

        if (gdbsig) {

            gdb_handlesig(cs, gdbsig);

            if (gdbsig != TARGET_SIGTRAP) {

                exit(EXIT_FAILURE);

            }

        }

        process_pending_signals(env);

    }

}


void msix_save(PCIDevice *dev, QEMUFile *f)

{

    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {

        return;

    }

    qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);

    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);

}


int qsv_init(AVCodecContext *s)

{

    InputStream *ist = s->opaque;

    QSVContext  *qsv = ist->hwaccel_ctx;

    AVQSVContext *hwctx_dec;

    int ret;

    if (!qsv) {

        av_log(NULL, AV_LOG_ERROR, "QSV transcoding is not initialized. "

               "-hwaccel qsv should only be used for one-to-one QSV transcoding "

               "with no filters.\n");

        return AVERROR_BUG;

    }

    ret = init_opaque_surf(qsv);

    if (ret < 0)

        return ret;

    hwctx_dec = av_qsv_alloc_context();

    if (!hwctx_dec)

        return AVERROR(ENOMEM);

    hwctx_dec->session        = qsv->session;

    hwctx_dec->iopattern      = MFX_IOPATTERN_OUT_OPAQUE_MEMORY;

    hwctx_dec->ext_buffers    = qsv->ext_buffers;

    hwctx_dec->nb_ext_buffers = FF_ARRAY_ELEMS(qsv->ext_buffers);

    av_freep(&s->hwaccel_context);

    s->hwaccel_context = hwctx_dec;

    ist->hwaccel_get_buffer = qsv_get_buffer;

    ist->hwaccel_uninit     = qsv_uninit;

    return 0;

}


static void default_drive(int enable, int snapshot, int use_scsi,

                          BlockInterfaceType type, int index,

                          const char *optstr)

{

    QemuOpts *opts;

    if (type == IF_DEFAULT) {

        type = use_scsi ? IF_SCSI : IF_IDE;

    }

    if (!enable || drive_get_by_index(type, index)) {

        return;

    }

    opts = drive_add(type, index, NULL, optstr);

    if (snapshot) {

        drive_enable_snapshot(opts, NULL);

    }

    if (!drive_init(opts, use_scsi)) {

        exit(1);

    }

}


void css_generate_css_crws(uint8_t cssid)

{

    if (!channel_subsys.sei_pending) {

        css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, cssid);

    }

    channel_subsys.sei_pending = true;

}


int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque)

{

    WaitObjects *w = &wait_objects;

    if (w->num >= MAXIMUM_WAIT_OBJECTS)

        return -1;

    w->events[w->num] = handle;

    w->func[w->num] = func;

    w->opaque[w->num] = opaque;

    w->num++;

    return 0;

}


static void scsi_device_unrealize(SCSIDevice *s, Error **errp)

{

    SCSIDeviceClass *sc = SCSI_DEVICE_GET_CLASS(s);

    if (sc->unrealize) {

        sc->unrealize(s, errp);

    }

}


void disas(FILE *out, void *code, unsigned long size)

{

    unsigned long pc;

    int count;

    struct disassemble_info disasm_info;

    int (*print_insn)(bfd_vma pc, disassemble_info *info);

    INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);

    disasm_info.buffer = code;

    disasm_info.buffer_vma = (unsigned long)code;

    disasm_info.buffer_length = size;

#ifdef HOST_WORDS_BIGENDIAN

    disasm_info.endian = BFD_ENDIAN_BIG;

#else

    disasm_info.endian = BFD_ENDIAN_LITTLE;

#endif

#if defined(__i386__)

    disasm_info.mach = bfd_mach_i386_i386;

    print_insn = print_insn_i386;

#elif defined(__x86_64__)

    disasm_info.mach = bfd_mach_x86_64;

    print_insn = print_insn_i386;

#elif defined(_ARCH_PPC)

    print_insn = print_insn_ppc;

#elif defined(__alpha__)

    print_insn = print_insn_alpha;

#elif defined(__sparc__)

    print_insn = print_insn_sparc;

#if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)

    disasm_info.mach = bfd_mach_sparc_v9b;

#endif

#elif defined(__arm__)

    print_insn = print_insn_arm;

#elif defined(__MIPSEB__)

    print_insn = print_insn_big_mips;

#elif defined(__MIPSEL__)

    print_insn = print_insn_little_mips;

#elif defined(__m68k__)

    print_insn = print_insn_m68k;

#elif defined(__s390__)

    print_insn = print_insn_s390;

#elif defined(__hppa__)

    print_insn = print_insn_hppa;

#elif defined(__ia64__)

    print_insn = print_insn_ia64;

#else

    fprintf(out, "0x%lx: Asm output not supported on this arch\n",

	    (long) code);

    return;

#endif

    for (pc = (unsigned long)code; size > 0; pc += count, size -= count) {

	fprintf(out, "0x%08lx:  ", pc);

#ifdef __arm__

        /* since data is included in the code, it is better to

           display code data too */

        fprintf(out, "%08x  ", (int)bfd_getl32((const bfd_byte *)pc));

#endif

	count = print_insn(pc, &disasm_info);

	fprintf(out, "\n");

	if (count < 0)

	    break;

    }

}


void bdrv_add_key(BlockDriverState *bs, const char *key, Error **errp)

{

    if (key) {

        if (!bdrv_is_encrypted(bs)) {

            error_setg(errp, "Node '%s' is not encrypted",

                      bdrv_get_device_or_node_name(bs));

        } else if (bdrv_set_key(bs, key) < 0) {

            error_set(errp, QERR_INVALID_PASSWORD);

        }

    } else {

        if (bdrv_key_required(bs)) {

            error_set(errp, ERROR_CLASS_DEVICE_ENCRYPTED,

                      "'%s' (%s) is encrypted",

                      bdrv_get_device_or_node_name(bs),

                      bdrv_get_encrypted_filename(bs));

        }

    }

}


static void armv7m_nvic_reset(DeviceState *dev)

{

    nvic_state *s = NVIC(dev);

    NVICClass *nc = NVIC_GET_CLASS(s);

    nc->parent_reset(dev);

    /* Common GIC reset resets to disabled; the NVIC doesn't have

     * per-CPU interfaces so mark our non-existent CPU interface

     * as enabled by default, and with a priority mask which allows

     * all interrupts through.

     */

    s->gic.cpu_enabled[0] = true;

    s->gic.priority_mask[0] = 0x100;

    /* The NVIC as a whole is always enabled. */

    s->gic.enabled = true;

    systick_reset(s);

}


static void float_to_int16_sse(int16_t *dst, const float *src, long len){

    int i;

    for(i=0; i<len; i+=4) {

        asm volatile(

            "cvtps2pi    %1, %%mm0 \n\t"

            "cvtps2pi    %2, %%mm1 \n\t"

            "packssdw %%mm1, %%mm0 \n\t"

            "movq     %%mm0, %0    \n\t"

            :"=m"(dst[i])

            :"m"(src[i]), "m"(src[i+2])

        );

    }

    asm volatile("emms");

}


static int migration_rate_limit(void *opaque)

{

    MigrationState *s = opaque;

    int ret;

    ret = qemu_file_get_error(s->file);

    if (ret) {

        return ret;

    }

    if (s->bytes_xfer >= s->xfer_limit) {

        return 1;

    }

    return 0;

}


void cpu_interrupt(CPUState *env, int mask)

{

    int old_mask;

    old_mask = env->interrupt_request;

    env->interrupt_request |= mask;

#ifndef CONFIG_USER_ONLY

    /*

     * If called from iothread context, wake the target cpu in

     * case its halted.

     */

    if (!qemu_cpu_self(env)) {

        qemu_cpu_kick(env);

        return;

    }

#endif

    if (use_icount) {

        env->icount_decr.u16.high = 0xffff;

#ifndef CONFIG_USER_ONLY

        if (!can_do_io(env)

            && (mask & ~old_mask) != 0) {

            cpu_abort(env, "Raised interrupt while not in I/O function");

        }

#endif

    } else {

        cpu_unlink_tb(env);

    }

}


static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,

                                    int mem_index, TCGMemOp s_bits,

                                    tcg_insn_unit **label_ptr, int which)

{

    const TCGReg r0 = TCG_REG_L0;

    const TCGReg r1 = TCG_REG_L1;

    TCGType ttype = TCG_TYPE_I32;

    TCGType htype = TCG_TYPE_I32;

    int trexw = 0, hrexw = 0;

    if (TCG_TARGET_REG_BITS == 64) {

        if (TARGET_LONG_BITS == 64) {

            ttype = TCG_TYPE_I64;

            trexw = P_REXW;

        }

        if (TCG_TYPE_PTR == TCG_TYPE_I64) {

            htype = TCG_TYPE_I64;

            hrexw = P_REXW;

        }

    }

    tcg_out_mov(s, htype, r0, addrlo);

    tcg_out_mov(s, ttype, r1, addrlo);

    tcg_out_shifti(s, SHIFT_SHR + hrexw, r0,

                   TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);

    tgen_arithi(s, ARITH_AND + trexw, r1,

                TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);

    tgen_arithi(s, ARITH_AND + hrexw, r0,

                (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);

    tcg_out_modrm_sib_offset(s, OPC_LEA + hrexw, r0, TCG_AREG0, r0, 0,

                             offsetof(CPUArchState, tlb_table[mem_index][0])

                             + which);

    /* cmp 0(r0), r1 */

    tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0);

    /* Prepare for both the fast path add of the tlb addend, and the slow

       path function argument setup.  There are two cases worth note:

       For 32-bit guest and x86_64 host, MOVL zero-extends the guest address

       before the fastpath ADDQ below.  For 64-bit guest and x32 host, MOVQ

       copies the entire guest address for the slow path, while truncation

       for the 32-bit host happens with the fastpath ADDL below.  */

    tcg_out_mov(s, ttype, r1, addrlo);

    /* jne slow_path */

    tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);

    label_ptr[0] = s->code_ptr;

    s->code_ptr += 4;

    if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {

        /* cmp 4(r0), addrhi */

        tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4);

        /* jne slow_path */

        tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);

        label_ptr[1] = s->code_ptr;

        s->code_ptr += 4;

    }

    /* TLB Hit.  */

    /* add addend(r0), r1 */

    tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,

                         offsetof(CPUTLBEntry, addend) - which);

}


static inline void t_gen_sext(TCGv d, TCGv s, int size)

{

	if (size == 1)

		tcg_gen_ext8s_i32(d, s);

	else if (size == 2)

		tcg_gen_ext16s_i32(d, s);

	else if(GET_TCGV(d) != GET_TCGV(s))

		tcg_gen_mov_tl(d, s);

}


static int vio_make_devnode(VIOsPAPRDevice *dev,

                            void *fdt)

{

    VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)qdev_get_info(&dev->qdev);

    int vdevice_off, node_off, ret;

    char *dt_name;

    vdevice_off = fdt_path_offset(fdt, "/vdevice");

    if (vdevice_off < 0) {

        return vdevice_off;

    }

    dt_name = vio_format_dev_name(dev);

    if (!dt_name) {

        return -ENOMEM;

    }

    node_off = fdt_add_subnode(fdt, vdevice_off, dt_name);

    free(dt_name);

    if (node_off < 0) {

        return node_off;

    }

    ret = fdt_setprop_cell(fdt, node_off, "reg", dev->reg);

    if (ret < 0) {

        return ret;

    }

    if (info->dt_type) {

        ret = fdt_setprop_string(fdt, node_off, "device_type",

                                 info->dt_type);

        if (ret < 0) {

            return ret;

        }

    }

    if (info->dt_compatible) {

        ret = fdt_setprop_string(fdt, node_off, "compatible",

                                 info->dt_compatible);

        if (ret < 0) {

            return ret;

        }

    }

    if (dev->qirq) {

        uint32_t ints_prop[] = {cpu_to_be32(dev->vio_irq_num), 0};

        ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop,

                          sizeof(ints_prop));

        if (ret < 0) {

            return ret;

        }

    }

    if (dev->rtce_window_size) {

        uint32_t dma_prop[] = {cpu_to_be32(dev->reg),

                               0, 0,

                               0, cpu_to_be32(dev->rtce_window_size)};

        ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);

        if (ret < 0) {

            return ret;

        }

        ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);

        if (ret < 0) {

            return ret;

        }

        ret = fdt_setprop(fdt, node_off, "ibm,my-dma-window", dma_prop,

                          sizeof(dma_prop));

        if (ret < 0) {

            return ret;

        }

    }

    if (info->devnode) {

        ret = (info->devnode)(dev, fdt, node_off);

        if (ret < 0) {

            return ret;

        }

    }

    return node_off;

}


void mkimg(const char *file, const char *fmt, unsigned size_mb)

{

    gchar *cli;

    bool ret;

    int rc;

    GError *err = NULL;

    char *qemu_img_path;

    gchar *out, *out2;

    char *abs_path;

    qemu_img_path = getenv("QTEST_QEMU_IMG");

    abs_path = realpath(qemu_img_path, NULL);

    assert(qemu_img_path);

    cli = g_strdup_printf("%s create -f %s %s %uM", abs_path,

                          fmt, file, size_mb);

    ret = g_spawn_command_line_sync(cli, &out, &out2, &rc, &err);

    if (err) {

        fprintf(stderr, "%s\n", err->message);

        g_error_free(err);

    }

    g_assert(ret && !err);

    /* In glib 2.34, we have g_spawn_check_exit_status. in 2.12, we don't.

     * glib 2.43.91 implementation assumes that any non-zero is an error for

     * windows, but uses extra precautions for Linux. However,

     * 0 is only possible if the program exited normally, so that should be

     * sufficient for our purposes on all platforms, here. */

    if (rc) {

        fprintf(stderr, "qemu-img returned status code %d\n", rc);

    }

    g_assert(!rc);

    g_free(out);

    g_free(out2);

    g_free(cli);

    free(abs_path);

}


static inline void RENAME(rgb32tobgr15)(const uint8_t *src, uint8_t *dst, long src_size)

{

    const uint8_t *s = src;

    const uint8_t *end;

#if COMPILE_TEMPLATE_MMX

    const uint8_t *mm_end;

#endif

    uint16_t *d = (uint16_t *)dst;

    end = s + src_size;

#if COMPILE_TEMPLATE_MMX

    __asm__ volatile(PREFETCH"    %0"::"m"(*src):"memory");

    __asm__ volatile(

        "movq          %0, %%mm7    \n\t"

        "movq          %1, %%mm6    \n\t"

        ::"m"(red_15mask),"m"(green_15mask));

    mm_end = end - 15;

    while (s < mm_end) {

        __asm__ volatile(

            PREFETCH"    32%1           \n\t"

            "movd          %1, %%mm0    \n\t"

            "movd         4%1, %%mm3    \n\t"

            "punpckldq    8%1, %%mm0    \n\t"

            "punpckldq   12%1, %%mm3    \n\t"

            "movq       %%mm0, %%mm1    \n\t"

            "movq       %%mm0, %%mm2    \n\t"

            "movq       %%mm3, %%mm4    \n\t"

            "movq       %%mm3, %%mm5    \n\t"

            "psllq         $7, %%mm0    \n\t"

            "psllq         $7, %%mm3    \n\t"

            "pand       %%mm7, %%mm0    \n\t"

            "pand       %%mm7, %%mm3    \n\t"

            "psrlq         $6, %%mm1    \n\t"

            "psrlq         $6, %%mm4    \n\t"

            "pand       %%mm6, %%mm1    \n\t"

            "pand       %%mm6, %%mm4    \n\t"

            "psrlq        $19, %%mm2    \n\t"

            "psrlq        $19, %%mm5    \n\t"

            "pand          %2, %%mm2    \n\t"

            "pand          %2, %%mm5    \n\t"

            "por        %%mm1, %%mm0    \n\t"

            "por        %%mm4, %%mm3    \n\t"

            "por        %%mm2, %%mm0    \n\t"

            "por        %%mm5, %%mm3    \n\t"

            "psllq        $16, %%mm3    \n\t"

            "por        %%mm3, %%mm0    \n\t"

            MOVNTQ"     %%mm0, %0       \n\t"

            :"=m"(*d):"m"(*s),"m"(blue_15mask):"memory");

        d += 4;

        s += 16;

    }

    __asm__ volatile(SFENCE:::"memory");

    __asm__ volatile(EMMS:::"memory");

#endif

    while (s < end) {

        register int rgb = *(const uint32_t*)s; s += 4;

        *d++ = ((rgb&0xF8)<<7) + ((rgb&0xF800)>>6) + ((rgb&0xF80000)>>19);

    }

}


static void cris_alu_op_exec(DisasContext *dc, int op,

                   TCGv dst, TCGv a, TCGv b, int size)

{

    /* Emit the ALU insns.  */

    switch (op) {

    case CC_OP_ADD:

        tcg_gen_add_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_addx_carry(dc, dst);

        break;

    case CC_OP_ADDC:

        tcg_gen_add_tl(dst, a, b);

        t_gen_add_flag(dst, 0); /* C_FLAG.  */

        break;

    case CC_OP_MCP:

        tcg_gen_add_tl(dst, a, b);

        t_gen_add_flag(dst, 8); /* R_FLAG.  */

        break;

    case CC_OP_SUB:

        tcg_gen_sub_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    case CC_OP_MOVE:

        tcg_gen_mov_tl(dst, b);

        break;

    case CC_OP_OR:

        tcg_gen_or_tl(dst, a, b);

        break;

    case CC_OP_AND:

        tcg_gen_and_tl(dst, a, b);

        break;

    case CC_OP_XOR:

        tcg_gen_xor_tl(dst, a, b);

        break;

    case CC_OP_LSL:

        t_gen_lsl(dst, a, b);

        break;

    case CC_OP_LSR:

        t_gen_lsr(dst, a, b);

        break;

    case CC_OP_ASR:

        t_gen_asr(dst, a, b);

        break;

    case CC_OP_NEG:

        tcg_gen_neg_tl(dst, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    case CC_OP_LZ:

        gen_helper_lz(dst, b);

        break;

    case CC_OP_MULS:

        tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);

        break;

    case CC_OP_MULU:

        tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);

        break;

    case CC_OP_DSTEP:

        t_gen_cris_dstep(dst, a, b);

        break;

    case CC_OP_MSTEP:

        t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);

        break;

    case CC_OP_BOUND:

    {

        int l1;

        l1 = gen_new_label();

        tcg_gen_mov_tl(dst, a);

        tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);

        tcg_gen_mov_tl(dst, b);

        gen_set_label(l1);

    }

        break;

    case CC_OP_CMP:

        tcg_gen_sub_tl(dst, a, b);

        /* Extended arithmetics.  */

        t_gen_subx_carry(dc, dst);

        break;

    default:

        qemu_log("illegal ALU op.\n");

        BUG();

        break;

    }

    if (size == 1) {

        tcg_gen_andi_tl(dst, dst, 0xff);

    } else if (size == 2) {

        tcg_gen_andi_tl(dst, dst, 0xffff);

    }

}


static void blockdev_backup_prepare(BlkTransactionState *common, Error **errp)

{

    BlockdevBackupState *state = DO_UPCAST(BlockdevBackupState, common, common);

    BlockdevBackup *backup;

    BlockBackend *blk, *target;

    Error *local_err = NULL;

    assert(common->action->kind == TRANSACTION_ACTION_KIND_BLOCKDEV_BACKUP);

    backup = common->action->blockdev_backup;

    blk = blk_by_name(backup->device);

    if (!blk) {

        error_setg(errp, "Device '%s' not found", backup->device);

        return;

    }

    if (!blk_is_available(blk)) {

        error_setg(errp, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);

        return;

    }

    target = blk_by_name(backup->target);

    if (!target) {

        error_setg(errp, "Device '%s' not found", backup->target);

        return;

    }

    /* AioContext is released in .clean() */

    state->aio_context = blk_get_aio_context(blk);

    if (state->aio_context != blk_get_aio_context(target)) {

        state->aio_context = NULL;

        error_setg(errp, "Backup between two IO threads is not implemented");

        return;

    }

    aio_context_acquire(state->aio_context);

    state->bs = blk_bs(blk);

    bdrv_drained_begin(state->bs);

    qmp_blockdev_backup(backup->device, backup->target,

                        backup->sync,

                        backup->has_speed, backup->speed,

                        backup->has_on_source_error, backup->on_source_error,

                        backup->has_on_target_error, backup->on_target_error,

                        &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }

    state->job = state->bs->job;

}


static int zipl_magic(uint8_t *ptr)

{

    uint32_t *p = (void*)ptr;

    uint32_t *z = (void*)ZIPL_MAGIC;

    if (*p != *z) {

        debug_print_int("invalid magic", *p);

        virtio_panic("invalid magic");

    }

    return 1;

}


static void bt_hid_interrupt_sdu(void *opaque, const uint8_t *data, int len)

{

    struct bt_hid_device_s *hid = opaque;

    if (len > BT_HID_MTU || len < 1)

        goto bad;

    if ((data[0] & 3) != BT_DATA_OUTPUT)

        goto bad;

    if ((data[0] >> 4) == BT_DATA) {

        if (hid->intr_state)

            goto bad;

        hid->data_type = BT_DATA_OUTPUT;

        hid->intrdataout.len = 0;

    } else if ((data[0] >> 4) == BT_DATC) {

        if (!hid->intr_state)

            goto bad;

    } else

        goto bad;

    memcpy(hid->intrdataout.buffer + hid->intrdataout.len, data + 1, len - 1);

    hid->intrdataout.len += len - 1;

    hid->intr_state = (len == BT_HID_MTU);

    if (!hid->intr_state) {

        memcpy(hid->dataout.buffer, hid->intrdataout.buffer,

                        hid->dataout.len = hid->intrdataout.len);

        bt_hid_out(hid);

    }

    return;

bad:

    fprintf(stderr, "%s: bad transaction on Interrupt channel.\n",

                    __func__);

}


static void decode_opc (CPUState *env, DisasContext *ctx)

{

    int32_t offset;

    int rs, rt, rd, sa;

    uint32_t op, op1, op2;

    int16_t imm;

    /* make sure instructions are on a word boundary */

    if (ctx->pc & 0x3) {

        env->CP0_BadVAddr = ctx->pc;

        generate_exception(ctx, EXCP_AdEL);

        return;

    }

    if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {

        int l1;

        /* Handle blikely not taken case */

        MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);

        l1 = gen_new_label();

        gen_op_jnz_T2(l1);

        gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);

        gen_goto_tb(ctx, 1, ctx->pc + 4);

        gen_set_label(l1);

    }

    op = MASK_OP_MAJOR(ctx->opcode);

    rs = (ctx->opcode >> 21) & 0x1f;

    rt = (ctx->opcode >> 16) & 0x1f;

    rd = (ctx->opcode >> 11) & 0x1f;

    sa = (ctx->opcode >> 6) & 0x1f;

    imm = (int16_t)ctx->opcode;

    switch (op) {

    case OPC_SPECIAL:

        op1 = MASK_SPECIAL(ctx->opcode);

        switch (op1) {

        case OPC_SLL:          /* Arithmetic with immediate */

        case OPC_SRL ... OPC_SRA:

            gen_arith_imm(env, ctx, op1, rd, rt, sa);

            break;

        case OPC_MOVZ ... OPC_MOVN:

            check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);

        case OPC_SLLV:         /* Arithmetic */

        case OPC_SRLV ... OPC_SRAV:

        case OPC_ADD ... OPC_NOR:

        case OPC_SLT ... OPC_SLTU:

            gen_arith(env, ctx, op1, rd, rs, rt);

            break;

        case OPC_MULT ... OPC_DIVU:

            gen_muldiv(ctx, op1, rs, rt);

            break;

        case OPC_JR ... OPC_JALR:

            gen_compute_branch(ctx, op1, rs, rd, sa);

            return;

        case OPC_TGE ... OPC_TEQ: /* Traps */

        case OPC_TNE:

            gen_trap(ctx, op1, rs, rt, -1);

            break;

        case OPC_MFHI:          /* Move from HI/LO */

        case OPC_MFLO:

            gen_HILO(ctx, op1, rd);

            break;

        case OPC_MTHI:

        case OPC_MTLO:          /* Move to HI/LO */

            gen_HILO(ctx, op1, rs);

            break;

        case OPC_PMON:          /* Pmon entry point, also R4010 selsl */

#ifdef MIPS_STRICT_STANDARD

            MIPS_INVAL("PMON / selsl");

            generate_exception(ctx, EXCP_RI);

#else

            gen_op_pmon(sa);

#endif

            break;

        case OPC_SYSCALL:

            generate_exception(ctx, EXCP_SYSCALL);

            break;

        case OPC_BREAK:

            generate_exception(ctx, EXCP_BREAK);

            break;

        case OPC_SPIM:

#ifdef MIPS_STRICT_STANDARD

            MIPS_INVAL("SPIM");

            generate_exception(ctx, EXCP_RI);

#else

           /* Implemented as RI exception for now. */

            MIPS_INVAL("spim (unofficial)");

            generate_exception(ctx, EXCP_RI);

#endif

            break;

        case OPC_SYNC:

            /* Treat as NOP. */

            break;

        case OPC_MOVCI:

            check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);

            if (env->CP0_Config1 & (1 << CP0C1_FP)) {

                save_cpu_state(ctx, 1);

                check_cp1_enabled(ctx);

                gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,

                          (ctx->opcode >> 16) & 1);

            } else {

                generate_exception_err(ctx, EXCP_CpU, 1);

            }

            break;

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

       /* MIPS64 specific opcodes */

        case OPC_DSLL:

        case OPC_DSRL ... OPC_DSRA:

        case OPC_DSLL32:

        case OPC_DSRL32 ... OPC_DSRA32:

            check_insn(env, ctx, ISA_MIPS3);

            check_mips_64(ctx);

            gen_arith_imm(env, ctx, op1, rd, rt, sa);

            break;

        case OPC_DSLLV:

        case OPC_DSRLV ... OPC_DSRAV:

        case OPC_DADD ... OPC_DSUBU:

            check_insn(env, ctx, ISA_MIPS3);

            check_mips_64(ctx);

            gen_arith(env, ctx, op1, rd, rs, rt);

            break;

        case OPC_DMULT ... OPC_DDIVU:

            check_insn(env, ctx, ISA_MIPS3);

            check_mips_64(ctx);

            gen_muldiv(ctx, op1, rs, rt);

            break;

#endif

        default:            /* Invalid */

            MIPS_INVAL("special");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

    case OPC_SPECIAL2:

        op1 = MASK_SPECIAL2(ctx->opcode);

        switch (op1) {

        case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */

        case OPC_MSUB ... OPC_MSUBU:

            check_insn(env, ctx, ISA_MIPS32);

            gen_muldiv(ctx, op1, rs, rt);

            break;

        case OPC_MUL:

            gen_arith(env, ctx, op1, rd, rs, rt);

            break;

        case OPC_CLZ ... OPC_CLO:

            check_insn(env, ctx, ISA_MIPS32);

            gen_cl(ctx, op1, rd, rs);

            break;

        case OPC_SDBBP:

            /* XXX: not clear which exception should be raised

             *      when in debug mode...

             */

            check_insn(env, ctx, ISA_MIPS32);

            if (!(ctx->hflags & MIPS_HFLAG_DM)) {

                generate_exception(ctx, EXCP_DBp);

            } else {

                generate_exception(ctx, EXCP_DBp);

            }

            /* Treat as NOP. */

            break;

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

        case OPC_DCLZ ... OPC_DCLO:

            check_insn(env, ctx, ISA_MIPS64);

            check_mips_64(ctx);

            gen_cl(ctx, op1, rd, rs);

            break;

#endif

        default:            /* Invalid */

            MIPS_INVAL("special2");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

    case OPC_SPECIAL3:

         op1 = MASK_SPECIAL3(ctx->opcode);

         switch (op1) {

         case OPC_EXT:

         case OPC_INS:

             check_insn(env, ctx, ISA_MIPS32R2);

             gen_bitops(ctx, op1, rt, rs, sa, rd);

             break;

         case OPC_BSHFL:

             check_insn(env, ctx, ISA_MIPS32R2);

             op2 = MASK_BSHFL(ctx->opcode);

             switch (op2) {

             case OPC_WSBH:

                 GEN_LOAD_REG_TN(T1, rt);

                 gen_op_wsbh();

                 break;

             case OPC_SEB:

                 GEN_LOAD_REG_TN(T1, rt);

                 gen_op_seb();

                 break;

             case OPC_SEH:

                 GEN_LOAD_REG_TN(T1, rt);

                 gen_op_seh();

                 break;

             default:            /* Invalid */

                 MIPS_INVAL("bshfl");

                 generate_exception(ctx, EXCP_RI);

                 break;

            }

            GEN_STORE_TN_REG(rd, T0);

            break;

        case OPC_RDHWR:

            check_insn(env, ctx, ISA_MIPS32R2);

            switch (rd) {

            case 0:

                save_cpu_state(ctx, 1);

                gen_op_rdhwr_cpunum();

                break;

            case 1:

                save_cpu_state(ctx, 1);

                gen_op_rdhwr_synci_step();

                break;

            case 2:

                save_cpu_state(ctx, 1);

                gen_op_rdhwr_cc();

                break;

            case 3:

                save_cpu_state(ctx, 1);

                gen_op_rdhwr_ccres();

                break;

            case 29:

#if defined (CONFIG_USER_ONLY)

                gen_op_tls_value();

                break;

#endif

            default:            /* Invalid */

                MIPS_INVAL("rdhwr");

                generate_exception(ctx, EXCP_RI);

                break;

            }

            GEN_STORE_TN_REG(rt, T0);

            break;

        case OPC_FORK:

            check_mips_mt(env, ctx);

            GEN_LOAD_REG_TN(T0, rt);

            GEN_LOAD_REG_TN(T1, rs);

            gen_op_fork();

            break;

        case OPC_YIELD:

            check_mips_mt(env, ctx);

            GEN_LOAD_REG_TN(T0, rs);

            gen_op_yield();

            GEN_STORE_TN_REG(rd, T0);

            break;

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

        case OPC_DEXTM ... OPC_DEXT:

        case OPC_DINSM ... OPC_DINS:

            check_insn(env, ctx, ISA_MIPS64R2);

            check_mips_64(ctx);

            gen_bitops(ctx, op1, rt, rs, sa, rd);

            break;

        case OPC_DBSHFL:

            check_insn(env, ctx, ISA_MIPS64R2);

            check_mips_64(ctx);

            op2 = MASK_DBSHFL(ctx->opcode);

            switch (op2) {

            case OPC_DSBH:

                GEN_LOAD_REG_TN(T1, rt);

                gen_op_dsbh();

                break;

            case OPC_DSHD:

                GEN_LOAD_REG_TN(T1, rt);

                gen_op_dshd();

                break;

            default:            /* Invalid */

                MIPS_INVAL("dbshfl");

                generate_exception(ctx, EXCP_RI);

                break;

            }

            GEN_STORE_TN_REG(rd, T0);

#endif

        default:            /* Invalid */

            MIPS_INVAL("special3");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

    case OPC_REGIMM:

        op1 = MASK_REGIMM(ctx->opcode);

        switch (op1) {

        case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */

        case OPC_BLTZAL ... OPC_BGEZALL:

            gen_compute_branch(ctx, op1, rs, -1, imm << 2);

            return;

        case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */

        case OPC_TNEI:

            gen_trap(ctx, op1, rs, -1, imm);

            break;

        case OPC_SYNCI:

            check_insn(env, ctx, ISA_MIPS32R2);

            /* Treat as NOP. */

            break;

        default:            /* Invalid */

            MIPS_INVAL("regimm");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

    case OPC_CP0:

        check_cp0_enabled(ctx);

        op1 = MASK_CP0(ctx->opcode);

        switch (op1) {

        case OPC_MFC0:

        case OPC_MTC0:

        case OPC_MFTR:

        case OPC_MTTR:

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

        case OPC_DMFC0:

        case OPC_DMTC0:

#endif

            gen_cp0(env, ctx, op1, rt, rd);

            break;

        case OPC_C0_FIRST ... OPC_C0_LAST:

            gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);

            break;

        case OPC_MFMC0:

            op2 = MASK_MFMC0(ctx->opcode);

            switch (op2) {

            case OPC_DMT:

                check_mips_mt(env, ctx);

                gen_op_dmt();

                break;

            case OPC_EMT:

                check_mips_mt(env, ctx);

                gen_op_emt();

                break;

            case OPC_DVPE:

                check_mips_mt(env, ctx);

                gen_op_dvpe();

                break;

            case OPC_EVPE:

                check_mips_mt(env, ctx);

                gen_op_evpe();

                break;

            case OPC_DI:

                check_insn(env, ctx, ISA_MIPS32R2);

                save_cpu_state(ctx, 1);

                gen_op_di();

                /* Stop translation as we may have switched the execution mode */

                ctx->bstate = BS_STOP;

                break;

            case OPC_EI:

                check_insn(env, ctx, ISA_MIPS32R2);

                save_cpu_state(ctx, 1);

                gen_op_ei();

                /* Stop translation as we may have switched the execution mode */

                ctx->bstate = BS_STOP;

                break;

            default:            /* Invalid */

                MIPS_INVAL("mfmc0");

                generate_exception(ctx, EXCP_RI);

                break;

            }

            GEN_STORE_TN_REG(rt, T0);

            break;

        case OPC_RDPGPR:

            check_insn(env, ctx, ISA_MIPS32R2);

            GEN_LOAD_SRSREG_TN(T0, rt);

            GEN_STORE_TN_REG(rd, T0);

            break;

        case OPC_WRPGPR:

            check_insn(env, ctx, ISA_MIPS32R2);

            GEN_LOAD_REG_TN(T0, rt);

            GEN_STORE_TN_SRSREG(rd, T0);

            break;

        default:

            MIPS_INVAL("cp0");

            generate_exception(ctx, EXCP_RI);

            break;

        }

        break;

    case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */

         gen_arith_imm(env, ctx, op, rt, rs, imm);

         break;

    case OPC_J ... OPC_JAL: /* Jump */

         offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;

         gen_compute_branch(ctx, op, rs, rt, offset);

         return;

    case OPC_BEQ ... OPC_BGTZ: /* Branch */

    case OPC_BEQL ... OPC_BGTZL:

         gen_compute_branch(ctx, op, rs, rt, imm << 2);

         return;

    case OPC_LB ... OPC_LWR: /* Load and stores */

    case OPC_SB ... OPC_SW:

    case OPC_SWR:

    case OPC_LL:

    case OPC_SC:

         gen_ldst(ctx, op, rt, rs, imm);

         break;

    case OPC_CACHE:

        check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);

        /* Treat as NOP. */

        break;

    case OPC_PREF:

        check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);

        /* Treat as NOP. */

        break;

    /* Floating point (COP1). */

    case OPC_LWC1:

    case OPC_LDC1:

    case OPC_SWC1:

    case OPC_SDC1:

        if (env->CP0_Config1 & (1 << CP0C1_FP)) {

            save_cpu_state(ctx, 1);

            check_cp1_enabled(ctx);

            gen_flt_ldst(ctx, op, rt, rs, imm);

        } else {

            generate_exception_err(ctx, EXCP_CpU, 1);

        }

        break;

    case OPC_CP1:

        if (env->CP0_Config1 & (1 << CP0C1_FP)) {

            save_cpu_state(ctx, 1);

            check_cp1_enabled(ctx);

            op1 = MASK_CP1(ctx->opcode);

            switch (op1) {

            case OPC_MFHC1:

            case OPC_MTHC1:

                check_insn(env, ctx, ISA_MIPS32R2);

            case OPC_MFC1:

            case OPC_CFC1:

            case OPC_MTC1:

            case OPC_CTC1:

                gen_cp1(ctx, op1, rt, rd);

                break;

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

            case OPC_DMFC1:

            case OPC_DMTC1:

                check_insn(env, ctx, ISA_MIPS3);

                gen_cp1(ctx, op1, rt, rd);

                break;

#endif

            case OPC_BC1ANY2:

            case OPC_BC1ANY4:

                check_cp1_3d(env, ctx);

                /* fall through */

            case OPC_BC1:

                gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),

                                    (rt >> 2) & 0x7, imm << 2);

                return;

            case OPC_S_FMT:

            case OPC_D_FMT:

            case OPC_W_FMT:

            case OPC_L_FMT:

            case OPC_PS_FMT:

                gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,

                           (imm >> 8) & 0x7);

                break;

            default:

                MIPS_INVAL("cp1");

                generate_exception (ctx, EXCP_RI);

                break;

            }

        } else {

            generate_exception_err(ctx, EXCP_CpU, 1);

        }

        break;

    /* COP2.  */

    case OPC_LWC2:

    case OPC_LDC2:

    case OPC_SWC2:

    case OPC_SDC2:

    case OPC_CP2:

        /* COP2: Not implemented. */

        generate_exception_err(ctx, EXCP_CpU, 2);

        break;

    case OPC_CP3:

        if (env->CP0_Config1 & (1 << CP0C1_FP)) {

            save_cpu_state(ctx, 1);

            check_cp1_enabled(ctx);

            op1 = MASK_CP3(ctx->opcode);

            switch (op1) {

            case OPC_LWXC1:

            case OPC_LDXC1:

            case OPC_LUXC1:

            case OPC_SWXC1:

            case OPC_SDXC1:

            case OPC_SUXC1:

                gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);

                break;

            case OPC_PREFX:

                /* Treat as NOP. */

                break;

            case OPC_ALNV_PS:

            case OPC_MADD_S:

            case OPC_MADD_D:

            case OPC_MADD_PS:

            case OPC_MSUB_S:

            case OPC_MSUB_D:

            case OPC_MSUB_PS:

            case OPC_NMADD_S:

            case OPC_NMADD_D:

            case OPC_NMADD_PS:

            case OPC_NMSUB_S:

            case OPC_NMSUB_D:

            case OPC_NMSUB_PS:

                gen_flt3_arith(ctx, op1, sa, rs, rd, rt);

                break;

            default:

                MIPS_INVAL("cp3");

                generate_exception (ctx, EXCP_RI);

                break;

            }

        } else {

            generate_exception_err(ctx, EXCP_CpU, 1);

        }

        break;

#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)

    /* MIPS64 opcodes */

    case OPC_LWU:

    case OPC_LDL ... OPC_LDR:

    case OPC_SDL ... OPC_SDR:

    case OPC_LLD:

    case OPC_LD:

    case OPC_SCD:

    case OPC_SD:

        check_insn(env, ctx, ISA_MIPS3);

        check_mips_64(ctx);

        gen_ldst(ctx, op, rt, rs, imm);

        break;

    case OPC_DADDI ... OPC_DADDIU:

        check_insn(env, ctx, ISA_MIPS3);

        check_mips_64(ctx);

        gen_arith_imm(env, ctx, op, rt, rs, imm);

        break;

#endif

    case OPC_JALX:

        check_insn(env, ctx, ASE_MIPS16);

        /* MIPS16: Not implemented. */

    case OPC_MDMX:

        check_insn(env, ctx, ASE_MDMX);

        /* MDMX: Not implemented. */

    default:            /* Invalid */

        MIPS_INVAL("major opcode");

        generate_exception(ctx, EXCP_RI);

        break;

    }

    if (ctx->hflags & MIPS_HFLAG_BMASK) {

        int hflags = ctx->hflags & MIPS_HFLAG_BMASK;

        /* Branches completion */

        ctx->hflags &= ~MIPS_HFLAG_BMASK;

        ctx->bstate = BS_BRANCH;

        save_cpu_state(ctx, 0);

        switch (hflags) {

        case MIPS_HFLAG_B:

            /* unconditional branch */

            MIPS_DEBUG("unconditional branch");

            gen_goto_tb(ctx, 0, ctx->btarget);

            break;

        case MIPS_HFLAG_BL:

            /* blikely taken case */

            MIPS_DEBUG("blikely branch taken");

            gen_goto_tb(ctx, 0, ctx->btarget);

            break;

        case MIPS_HFLAG_BC:

            /* Conditional branch */

            MIPS_DEBUG("conditional branch");

            {

              int l1;

              l1 = gen_new_label();

              gen_op_jnz_T2(l1);

              gen_goto_tb(ctx, 1, ctx->pc + 4);

              gen_set_label(l1);

              gen_goto_tb(ctx, 0, ctx->btarget);

            }

            break;

        case MIPS_HFLAG_BR:

            /* unconditional branch to register */

            MIPS_DEBUG("branch to register");

            gen_op_breg();

            gen_op_reset_T0();

            gen_op_exit_tb();

            break;

        default:

            MIPS_DEBUG("unknown branch");

            break;

        }

    }

}


static void port92_write(void *opaque, hwaddr addr, uint64_t val,

                         unsigned size)

{

    Port92State *s = opaque;

    int oldval = s->outport;

    DPRINTF("port92: write 0x%02" PRIx64 "\n", val);

    s->outport = val;

    qemu_set_irq(*s->a20_out, (val >> 1) & 1);

    if ((val & 1) && !(oldval & 1)) {

        qemu_system_reset_request();

    }

}


static uint64_t coroutine_fn mirror_iteration(MirrorBlockJob *s)

{

    BlockDriverState *source = blk_bs(s->common.blk);

    int64_t sector_num, first_chunk;

    uint64_t delay_ns = 0;

    /* At least the first dirty chunk is mirrored in one iteration. */

    int nb_chunks = 1;

    int64_t end = s->bdev_length / BDRV_SECTOR_SIZE;

    int sectors_per_chunk = s->granularity >> BDRV_SECTOR_BITS;

    bool write_zeroes_ok = bdrv_can_write_zeroes_with_unmap(blk_bs(s->target));

    sector_num = hbitmap_iter_next(&s->hbi);

    if (sector_num < 0) {

        bdrv_dirty_iter_init(s->dirty_bitmap, &s->hbi);

        sector_num = hbitmap_iter_next(&s->hbi);

        trace_mirror_restart_iter(s, bdrv_get_dirty_count(s->dirty_bitmap));

        assert(sector_num >= 0);

    }

    first_chunk = sector_num / sectors_per_chunk;

    while (test_bit(first_chunk, s->in_flight_bitmap)) {

        trace_mirror_yield_in_flight(s, sector_num, s->in_flight);

        mirror_wait_for_io(s);

    }

    block_job_pause_point(&s->common);

    /* Find the number of consective dirty chunks following the first dirty

     * one, and wait for in flight requests in them. */

    while (nb_chunks * sectors_per_chunk < (s->buf_size >> BDRV_SECTOR_BITS)) {

        int64_t hbitmap_next;

        int64_t next_sector = sector_num + nb_chunks * sectors_per_chunk;

        int64_t next_chunk = next_sector / sectors_per_chunk;

        if (next_sector >= end ||

            !bdrv_get_dirty(source, s->dirty_bitmap, next_sector)) {

            break;

        }

        if (test_bit(next_chunk, s->in_flight_bitmap)) {

            break;

        }

        hbitmap_next = hbitmap_iter_next(&s->hbi);

        if (hbitmap_next > next_sector || hbitmap_next < 0) {

            /* The bitmap iterator's cache is stale, refresh it */

            bdrv_set_dirty_iter(&s->hbi, next_sector);

            hbitmap_next = hbitmap_iter_next(&s->hbi);

        }

        assert(hbitmap_next == next_sector);

        nb_chunks++;

    }

    /* Clear dirty bits before querying the block status, because

     * calling bdrv_get_block_status_above could yield - if some blocks are

     * marked dirty in this window, we need to know.

     */

    bdrv_reset_dirty_bitmap(s->dirty_bitmap, sector_num,

                            nb_chunks * sectors_per_chunk);

    bitmap_set(s->in_flight_bitmap, sector_num / sectors_per_chunk, nb_chunks);

    while (nb_chunks > 0 && sector_num < end) {

        int ret;

        int io_sectors, io_sectors_acct;

        BlockDriverState *file;

        enum MirrorMethod {

            MIRROR_METHOD_COPY,

            MIRROR_METHOD_ZERO,

            MIRROR_METHOD_DISCARD

        } mirror_method = MIRROR_METHOD_COPY;

        assert(!(sector_num % sectors_per_chunk));

        ret = bdrv_get_block_status_above(source, NULL, sector_num,

                                          nb_chunks * sectors_per_chunk,

                                          &io_sectors, &file);

        if (ret < 0) {

            io_sectors = nb_chunks * sectors_per_chunk;

        }

        io_sectors -= io_sectors % sectors_per_chunk;

        if (io_sectors < sectors_per_chunk) {

            io_sectors = sectors_per_chunk;

        } else if (ret >= 0 && !(ret & BDRV_BLOCK_DATA)) {

            int64_t target_sector_num;

            int target_nb_sectors;

            bdrv_round_sectors_to_clusters(blk_bs(s->target), sector_num,

                                           io_sectors,  &target_sector_num,

                                           &target_nb_sectors);

            if (target_sector_num == sector_num &&

                target_nb_sectors == io_sectors) {

                mirror_method = ret & BDRV_BLOCK_ZERO ?

                                    MIRROR_METHOD_ZERO :

                                    MIRROR_METHOD_DISCARD;

            }

        }

        while (s->in_flight >= MAX_IN_FLIGHT) {

            trace_mirror_yield_in_flight(s, sector_num, s->in_flight);

            mirror_wait_for_io(s);

        }

        mirror_clip_sectors(s, sector_num, &io_sectors);

        switch (mirror_method) {

        case MIRROR_METHOD_COPY:

            io_sectors = mirror_do_read(s, sector_num, io_sectors);

            io_sectors_acct = io_sectors;

            break;

        case MIRROR_METHOD_ZERO:

        case MIRROR_METHOD_DISCARD:

            mirror_do_zero_or_discard(s, sector_num, io_sectors,

                                      mirror_method == MIRROR_METHOD_DISCARD);

            if (write_zeroes_ok) {

                io_sectors_acct = 0;

            } else {

                io_sectors_acct = io_sectors;

            }

            break;

        default:

            abort();

        }

        assert(io_sectors);

        sector_num += io_sectors;

        nb_chunks -= DIV_ROUND_UP(io_sectors, sectors_per_chunk);

        if (s->common.speed) {

            delay_ns = ratelimit_calculate_delay(&s->limit, io_sectors_acct);

        }

    }

    return delay_ns;

}


static void flush_encoders(void)

{

    int i, ret;

    for (i = 0; i < nb_output_streams; i++) {

        OutputStream   *ost = output_streams[i];

        AVCodecContext *enc = ost->enc_ctx;

        AVFormatContext *os = output_files[ost->file_index]->ctx;

        int stop_encoding = 0;

        if (!ost->encoding_needed)

            continue;

        if (enc->codec_type == AVMEDIA_TYPE_AUDIO && enc->frame_size <= 1)

            continue;

        if (enc->codec_type != AVMEDIA_TYPE_VIDEO && enc->codec_type != AVMEDIA_TYPE_AUDIO)

            continue;

        avcodec_send_frame(enc, NULL);

        for (;;) {

            const char *desc = NULL;

            switch (enc->codec_type) {

            case AVMEDIA_TYPE_AUDIO:

                desc   = "Audio";

                break;

            case AVMEDIA_TYPE_VIDEO:

                desc   = "Video";

                break;

            default:

                av_assert0(0);

            }

            if (1) {

                AVPacket pkt;

                av_init_packet(&pkt);

                pkt.data = NULL;

                pkt.size = 0;

                ret = avcodec_receive_packet(enc, &pkt);

                if (ret < 0 && ret != AVERROR_EOF) {

                    av_log(NULL, AV_LOG_FATAL, "%s encoding failed\n", desc);

                    exit_program(1);

                }

                if (ost->logfile && enc->stats_out) {

                    fprintf(ost->logfile, "%s", enc->stats_out);

                }

                if (ret == AVERROR_EOF) {

                    stop_encoding = 1;

                    break;

                }

                av_packet_rescale_ts(&pkt, enc->time_base, ost->st->time_base);

                output_packet(os, &pkt, ost);

            }

            if (stop_encoding)

                break;

        }

    }

}


AVFormatContext *ff_rtp_chain_mux_open(AVFormatContext *s, AVStream *st,

                                       URLContext *handle, int packet_size)

{

    AVFormatContext *rtpctx;

    int ret;

    AVOutputFormat *rtp_format = av_guess_format("rtp", NULL, NULL);

    if (!rtp_format)

        return NULL;

    /* Allocate an AVFormatContext for each output stream */

    rtpctx = avformat_alloc_context();

    if (!rtpctx)

        return NULL;

    rtpctx->oformat = rtp_format;

    if (!av_new_stream(rtpctx, 0)) {

        av_free(rtpctx);

        return NULL;

    }

    /* Copy the max delay setting; the rtp muxer reads this. */

    rtpctx->max_delay = s->max_delay;

    /* Copy other stream parameters. */

    rtpctx->streams[0]->sample_aspect_ratio = st->sample_aspect_ratio;

    /* Set the synchronized start time. */

    rtpctx->start_time_realtime = s->start_time_realtime;

    avcodec_copy_context(rtpctx->streams[0]->codec, st->codec);

    if (handle) {

        url_fdopen(&rtpctx->pb, handle);

    } else

        url_open_dyn_packet_buf(&rtpctx->pb, packet_size);

    ret = av_write_header(rtpctx);

    if (ret) {

        if (handle) {

            avio_close(rtpctx->pb);

        } else {

            uint8_t *ptr;

            avio_close_dyn_buf(rtpctx->pb, &ptr);

            av_free(ptr);

        }

        avformat_free_context(rtpctx);

        return NULL;

    }

    return rtpctx;

}


static av_cold int avs_decode_init(AVCodecContext * avctx)

{

    AvsContext *s = avctx->priv_data;

    s->frame = av_frame_alloc();

    if (!s->frame)

        return AVERROR(ENOMEM);

    avctx->pix_fmt = AV_PIX_FMT_PAL8;

    ff_set_dimensions(avctx, 318, 198);

    return 0;

}


static av_cold int raw_encode_close(AVCodecContext *avctx)

{

    av_frame_free(&avctx->coded_frame);

    return 0;

}


int avio_close_dyn_buf(AVIOContext *s, uint8_t **pbuffer)

{

    DynBuffer *d;

    int size;

    static const char padbuf[AV_INPUT_BUFFER_PADDING_SIZE] = {0};

    int padding = 0;

    if (!s) {

        *pbuffer = NULL;

        return 0;

    }

    /* don't attempt to pad fixed-size packet buffers */

    if (!s->max_packet_size) {

        avio_write(s, padbuf, sizeof(padbuf));

        padding = AV_INPUT_BUFFER_PADDING_SIZE;

    }

    avio_flush(s);

    d = s->opaque;

    *pbuffer = d->buffer;

    size = d->size;

    av_free(d);

    av_free(s);

    return size - padding;

}


void pcie_port_init_reg(PCIDevice *d)

{

    /* Unlike pci bridge,

       66MHz and fast back to back don't apply to pci express port. */

    pci_set_word(d->config + PCI_STATUS, 0);

    pci_set_word(d->config + PCI_SEC_STATUS, 0);

    /* Unlike conventional pci bridge, some bits are hardwired to 0. */

#define  PCI_BRIDGE_CTL_VGA_16BIT       0x10    /* VGA 16-bit decode */

    pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,

                 PCI_BRIDGE_CTL_PARITY |

                 PCI_BRIDGE_CTL_ISA |

                 PCI_BRIDGE_CTL_VGA |

                 PCI_BRIDGE_CTL_VGA_16BIT | /* Req, but no alias support yet */

                 PCI_BRIDGE_CTL_SERR |

                 PCI_BRIDGE_CTL_BUS_RESET);

}


static void get_slice_data(ProresContext *ctx, const uint16_t *src,

                           int linesize, int x, int y, int w, int h,

                           DCTELEM *blocks, uint16_t *emu_buf,

                           int mbs_per_slice, int blocks_per_mb, int is_chroma)

{

    const uint16_t *esrc;

    const int mb_width = 4 * blocks_per_mb;

    int elinesize;

    int i, j, k;

    for (i = 0; i < mbs_per_slice; i++, src += mb_width) {

        if (x >= w) {

            memset(blocks, 0, 64 * (mbs_per_slice - i) * blocks_per_mb

                              * sizeof(*blocks));

            return;

        }

        if (x + mb_width <= w && y + 16 <= h) {

            esrc      = src;

            elinesize = linesize;

        } else {

            int bw, bh, pix;

            esrc      = emu_buf;

            elinesize = 16 * sizeof(*emu_buf);

            bw = FFMIN(w - x, mb_width);

            bh = FFMIN(h - y, 16);

            for (j = 0; j < bh; j++) {

                memcpy(emu_buf + j * 16,

                       (const uint8_t*)src + j * linesize,

                       bw * sizeof(*src));

                pix = emu_buf[j * 16 + bw - 1];

                for (k = bw; k < mb_width; k++)

                    emu_buf[j * 16 + k] = pix;

            }

            for (; j < 16; j++)

                memcpy(emu_buf + j * 16,

                       emu_buf + (bh - 1) * 16,

                       mb_width * sizeof(*emu_buf));

        }

        if (!is_chroma) {

            ctx->dsp.fdct(esrc, elinesize, blocks);

            blocks += 64;

            if (blocks_per_mb > 2) {

                ctx->dsp.fdct(src + 8, linesize, blocks);

                blocks += 64;

            }

            ctx->dsp.fdct(src + linesize * 4, linesize, blocks);

            blocks += 64;

            if (blocks_per_mb > 2) {

                ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);

                blocks += 64;

            }

        } else {

            ctx->dsp.fdct(esrc, elinesize, blocks);

            blocks += 64;

            ctx->dsp.fdct(src + linesize * 4, linesize, blocks);

            blocks += 64;

            if (blocks_per_mb > 2) {

                ctx->dsp.fdct(src + 8, linesize, blocks);

                blocks += 64;

                ctx->dsp.fdct(src + linesize * 4 + 8, linesize, blocks);

                blocks += 64;

            }

        }

        x += mb_width;

    }

}


static always_inline void gen_farith3 (void *helper,

                                       int ra, int rb, int rc)

{

    if (unlikely(rc == 31))

        return;

    if (ra != 31) {

        if (rb != 31)

            tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]);

        else {

            TCGv tmp = tcg_const_i64(0);

            tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp);

            tcg_temp_free(tmp);

        }

    } else {

        TCGv tmp = tcg_const_i64(0);

        if (rb != 31)

            tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]);

        else

            tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp);

        tcg_temp_free(tmp);

    }

}


static bool vfio_prereg_listener_skipped_section(MemoryRegionSection *section)

{

    if (memory_region_is_iommu(section->mr)) {

        hw_error("Cannot possibly preregister IOMMU memory");

    }

    return !memory_region_is_ram(section->mr) ||

            memory_region_is_skip_dump(section->mr);

}


static void gen_mtc0 (DisasContext *ctx, int reg, int sel)

{

    const char *rn = "invalid";

    switch (reg) {

    case 0:

        switch (sel) {

        case 0:

           gen_op_mtc0_index();

            rn = "Index";

            break;

        case 1:

//            gen_op_mtc0_mvpcontrol(); /* MT ASE */

            rn = "MVPControl";

//            break;

        case 2:

//            gen_op_mtc0_mvpconf0(); /* MT ASE */

            rn = "MVPConf0";

//            break;

        case 3:

//            gen_op_mtc0_mvpconf1(); /* MT ASE */

            rn = "MVPConf1";

//            break;

        default:

            goto die;

        }

        break;

    case 1:

        switch (sel) {

        case 0:

            /* ignored */

            rn = "Random";

            break;

        case 1:

//            gen_op_mtc0_vpecontrol(); /* MT ASE */

            rn = "VPEControl";

//            break;

        case 2:

//            gen_op_mtc0_vpeconf0(); /* MT ASE */

            rn = "VPEConf0";

//            break;

        case 3:

//            gen_op_mtc0_vpeconf1(); /* MT ASE */

            rn = "VPEConf1";

//            break;

        case 4:

//            gen_op_mtc0_YQMask(); /* MT ASE */

            rn = "YQMask";

//            break;

        case 5:

//            gen_op_mtc0_vpeschedule(); /* MT ASE */

            rn = "VPESchedule";

//            break;

        case 6:

//            gen_op_mtc0_vpeschefback(); /* MT ASE */

            rn = "VPEScheFBack";

//            break;

        case 7:

//            gen_op_mtc0_vpeopt(); /* MT ASE */

            rn = "VPEOpt";

//            break;

        default:

            goto die;

        }

        break;

    case 2:

        switch (sel) {

        case 0:

            gen_op_mtc0_entrylo0();

            rn = "EntryLo0";

            break;

        case 1:

//            gen_op_mtc0_tcstatus(); /* MT ASE */

            rn = "TCStatus";

//            break;

        case 2:

//            gen_op_mtc0_tcbind(); /* MT ASE */

            rn = "TCBind";

//            break;

        case 3:

//            gen_op_mtc0_tcrestart(); /* MT ASE */

            rn = "TCRestart";

//            break;

        case 4:

//            gen_op_mtc0_tchalt(); /* MT ASE */

            rn = "TCHalt";

//            break;

        case 5:

//            gen_op_mtc0_tccontext(); /* MT ASE */

            rn = "TCContext";

//            break;

        case 6:

//            gen_op_mtc0_tcschedule(); /* MT ASE */

            rn = "TCSchedule";

//            break;

        case 7:

//            gen_op_mtc0_tcschefback(); /* MT ASE */

            rn = "TCScheFBack";

//            break;

        default:

            goto die;

        }

        break;

    case 3:

        switch (sel) {

        case 0:

            gen_op_mtc0_entrylo1();

            rn = "EntryLo1";

            break;

        default:

            goto die;

        }

        break;

    case 4:

        switch (sel) {

        case 0:

            gen_op_mtc0_context();

            rn = "Context";

            break;

        case 1:

//            gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */

            rn = "ContextConfig";

//            break;

        default:

            goto die;

        }

        break;

    case 5:

        switch (sel) {

        case 0:

            gen_op_mtc0_pagemask();

            rn = "PageMask";

            break;

        case 1:

            gen_op_mtc0_pagegrain();

            rn = "PageGrain";

            break;

        default:

            goto die;

        }

        break;

    case 6:

        switch (sel) {

        case 0:

            gen_op_mtc0_wired();

            rn = "Wired";

            break;

        case 1:

//            gen_op_mtc0_srsconf0(); /* shadow registers */

            rn = "SRSConf0";

//            break;

        case 2:

//            gen_op_mtc0_srsconf1(); /* shadow registers */

            rn = "SRSConf1";

//            break;

        case 3:

//            gen_op_mtc0_srsconf2(); /* shadow registers */

            rn = "SRSConf2";

//            break;

        case 4:

//            gen_op_mtc0_srsconf3(); /* shadow registers */

            rn = "SRSConf3";

//            break;

        case 5:

//            gen_op_mtc0_srsconf4(); /* shadow registers */

            rn = "SRSConf4";

//            break;

        default:

            goto die;

        }

        break;

    case 7:

        switch (sel) {

        case 0:

            gen_op_mtc0_hwrena();

            rn = "HWREna";

            break;

        default:

            goto die;

        }

        break;

    case 8:

        /* ignored */

        rn = "BadVaddr";

        break;

    case 9:

        switch (sel) {

        case 0:

            gen_op_mtc0_count();

            rn = "Count";

            break;

        /* 6,7 are implementation dependent */

        default:

            goto die;

        }

        /* Stop translation as we may have switched the execution mode */

        ctx->bstate = BS_STOP;

        break;

    case 10:

        switch (sel) {

        case 0:

            gen_op_mtc0_entryhi();

            rn = "EntryHi";

            break;

        default:

            goto die;

        }

        break;

    case 11:

        switch (sel) {

        case 0:

            gen_op_mtc0_compare();

            rn = "Compare";

            break;

        /* 6,7 are implementation dependent */

        default:

            goto die;

        }

        /* Stop translation as we may have switched the execution mode */

        ctx->bstate = BS_STOP;

        break;

    case 12:

        switch (sel) {

        case 0:

            gen_op_mtc0_status();

            /* BS_STOP isn't good enough here, hflags may have changed. */

            gen_save_pc(ctx->pc + 4);

            ctx->bstate = BS_EXCP;

            rn = "Status";

            break;

        case 1:

            gen_op_mtc0_intctl();

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            rn = "IntCtl";

            break;

        case 2:

            gen_op_mtc0_srsctl();

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            rn = "SRSCtl";

            break;

        case 3:

            gen_op_mtc0_srsmap();

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            rn = "SRSMap";

            break;

        default:

            goto die;

        }

        break;

    case 13:

        switch (sel) {

        case 0:

            gen_op_mtc0_cause();

            rn = "Cause";

            break;

        default:

            goto die;

        }

        /* Stop translation as we may have switched the execution mode */

        ctx->bstate = BS_STOP;

        break;

    case 14:

        switch (sel) {

        case 0:

            gen_op_mtc0_epc();

            rn = "EPC";

            break;

        default:

            goto die;

        }

        break;

    case 15:

        switch (sel) {

        case 0:

            /* ignored */

            rn = "PRid";

            break;

        case 1:

            gen_op_mtc0_ebase();

            rn = "EBase";

            break;

        default:

            goto die;

        }

        break;

    case 16:

        switch (sel) {

        case 0:

            gen_op_mtc0_config0();

            rn = "Config";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            break;

        case 1:

            /* ignored, read only */

            rn = "Config1";

            break;

        case 2:

            gen_op_mtc0_config2();

            rn = "Config2";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            break;

        case 3:

            /* ignored, read only */

            rn = "Config3";

            break;

        /* 4,5 are reserved */

        /* 6,7 are implementation dependent */

        case 6:

            /* ignored */

            rn = "Config6";

            break;

        case 7:

            /* ignored */

            rn = "Config7";

            break;

        default:

            rn = "Invalid config selector";

            goto die;

        }

        break;

    case 17:

        switch (sel) {

        case 0:

            /* ignored */

            rn = "LLAddr";

            break;

        default:

            goto die;

        }

        break;

    case 18:

        switch (sel) {

        case 0 ... 7:

            gen_op_mtc0_watchlo(sel);

            rn = "WatchLo";

            break;

        default:

            goto die;

        }

        break;

    case 19:

        switch (sel) {

        case 0 ... 7:

            gen_op_mtc0_watchhi(sel);

            rn = "WatchHi";

            break;

        default:

            goto die;

        }

        break;

    case 20:

        switch (sel) {

        case 0:

#ifdef TARGET_MIPS64

            gen_op_mtc0_xcontext();

            rn = "XContext";

            break;

#endif

        default:

            goto die;

        }

        break;

    case 21:

       /* Officially reserved, but sel 0 is used for R1x000 framemask */

        switch (sel) {

        case 0:

            gen_op_mtc0_framemask();

            rn = "Framemask";

            break;

        default:

            goto die;

        }

        break;

    case 22:

        /* ignored */

        rn = "Diagnostic"; /* implementation dependent */

        break;

    case 23:

        switch (sel) {

        case 0:

            gen_op_mtc0_debug(); /* EJTAG support */

            /* BS_STOP isn't good enough here, hflags may have changed. */

            gen_save_pc(ctx->pc + 4);

            ctx->bstate = BS_EXCP;

            rn = "Debug";

            break;

        case 1:

//            gen_op_mtc0_tracecontrol(); /* PDtrace support */

            rn = "TraceControl";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

//            break;

        case 2:

//            gen_op_mtc0_tracecontrol2(); /* PDtrace support */

            rn = "TraceControl2";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

//            break;

        case 3:

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

//            gen_op_mtc0_usertracedata(); /* PDtrace support */

            rn = "UserTraceData";

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

//            break;

        case 4:

//            gen_op_mtc0_debug(); /* PDtrace support */

            /* Stop translation as we may have switched the execution mode */

            ctx->bstate = BS_STOP;

            rn = "TraceBPC";

//            break;

        default:

            goto die;

        }

        break;

    case 24:

        switch (sel) {

        case 0:

            gen_op_mtc0_depc(); /* EJTAG support */

            rn = "DEPC";

            break;

        default:

            goto die;

        }

        break;

    case 25:

        switch (sel) {

        case 0:

            gen_op_mtc0_performance0();

            rn = "Performance0";

            break;

        case 1:

//            gen_op_mtc0_performance1();

            rn = "Performance1";

//            break;

        case 2:

//            gen_op_mtc0_performance2();

            rn = "Performance2";

//            break;

        case 3:

//            gen_op_mtc0_performance3();

            rn = "Performance3";

//            break;

        case 4:

//            gen_op_mtc0_performance4();

            rn = "Performance4";

//            break;

        case 5:

//            gen_op_mtc0_performance5();

            rn = "Performance5";

//            break;

        case 6:

//            gen_op_mtc0_performance6();

            rn = "Performance6";

//            break;

        case 7:

//            gen_op_mtc0_performance7();

            rn = "Performance7";

//            break;

        default:

            goto die;

        }

       break;

    case 26:

        /* ignored */

        rn = "ECC";

        break;

    case 27:

        switch (sel) {

        case 0 ... 3:

            /* ignored */

            rn = "CacheErr";

            break;

        default:

            goto die;

        }

       break;

    case 28:

        switch (sel) {

        case 0:

        case 2:

        case 4:

        case 6:

            gen_op_mtc0_taglo();

            rn = "TagLo";

            break;

        case 1:

        case 3:

        case 5:

        case 7:

            gen_op_mtc0_datalo();

            rn = "DataLo";

            break;

        default:

            goto die;

        }

        break;

    case 29:

        switch (sel) {

        case 0:

        case 2:

        case 4:

        case 6:

            gen_op_mtc0_taghi();

            rn = "TagHi";

            break;

        case 1:

        case 3:

        case 5:

        case 7:

            gen_op_mtc0_datahi();

            rn = "DataHi";

            break;

        default:

            rn = "invalid sel";

            goto die;

        }

       break;

    case 30:

        switch (sel) {

        case 0:

            gen_op_mtc0_errorepc();

            rn = "ErrorEPC";

            break;

        default:

            goto die;

        }

        break;

    case 31:

        switch (sel) {

        case 0:

            gen_op_mtc0_desave(); /* EJTAG support */

            rn = "DESAVE";

            break;

        default:

            goto die;

        }

        /* Stop translation as we may have switched the execution mode */

        ctx->bstate = BS_STOP;

        break;

    default:

       goto die;

    }

#if defined MIPS_DEBUG_DISAS

    if (loglevel & CPU_LOG_TB_IN_ASM) {

        fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",

                rn, reg, sel);

    }

#endif

    return;

die:

#if defined MIPS_DEBUG_DISAS

    if (loglevel & CPU_LOG_TB_IN_ASM) {

        fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",

                rn, reg, sel);

    }

#endif

    generate_exception(ctx, EXCP_RI);

}


static void test_native_list_integer_helper(TestInputVisitorData *data,

                                            const void *unused,

                                            UserDefNativeListUnionKind kind)

{

    UserDefNativeListUnion *cvalue = NULL;

    Visitor *v;

    GString *gstr_list = g_string_new("");

    GString *gstr_union = g_string_new("");

    int i;

    for (i = 0; i < 32; i++) {

        g_string_append_printf(gstr_list, "%d", i);

        if (i != 31) {

            g_string_append(gstr_list, ", ");

        }

    }

    g_string_append_printf(gstr_union,  "{ 'type': '%s', 'data': [ %s ] }",

                           UserDefNativeListUnionKind_lookup[kind],

                           gstr_list->str);

    v = visitor_input_test_init_raw(data,  gstr_union->str);

    visit_type_UserDefNativeListUnion(v, NULL, &cvalue, &error_abort);

    g_assert(cvalue != NULL);

    g_assert_cmpint(cvalue->type, ==, kind);

    switch (kind) {

    case USER_DEF_NATIVE_LIST_UNION_KIND_INTEGER: {

        intList *elem = NULL;

        for (i = 0, elem = cvalue->u.integer.data;

             elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_S8: {

        int8List *elem = NULL;

        for (i = 0, elem = cvalue->u.s8.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_S16: {

        int16List *elem = NULL;

        for (i = 0, elem = cvalue->u.s16.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_S32: {

        int32List *elem = NULL;

        for (i = 0, elem = cvalue->u.s32.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_S64: {

        int64List *elem = NULL;

        for (i = 0, elem = cvalue->u.s64.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_U8: {

        uint8List *elem = NULL;

        for (i = 0, elem = cvalue->u.u8.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_U16: {

        uint16List *elem = NULL;

        for (i = 0, elem = cvalue->u.u16.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_U32: {

        uint32List *elem = NULL;

        for (i = 0, elem = cvalue->u.u32.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    case USER_DEF_NATIVE_LIST_UNION_KIND_U64: {

        uint64List *elem = NULL;

        for (i = 0, elem = cvalue->u.u64.data; elem; elem = elem->next, i++) {

            g_assert_cmpint(elem->value, ==, i);

        }

        break;

    }

    default:

        g_assert_not_reached();

    }

    g_string_free(gstr_union, true);

    g_string_free(gstr_list, true);

    qapi_free_UserDefNativeListUnion(cvalue);

}


pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)

{

    int i;

    uint32_t txr_len_log2, rxr_len_log2;

    uint32_t req_ring_size, cmp_ring_size;

    m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;

    if ((ri->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)

        || (ri->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES)) {

        return -1;

    }

    req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;

    cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;

    txr_len_log2 = pvscsi_log2(req_ring_size - 1);

    rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);

    m->txr_len_mask = MASK(txr_len_log2);

    m->rxr_len_mask = MASK(rxr_len_log2);

    m->consumed_ptr = 0;

    m->filled_cmp_ptr = 0;

    for (i = 0; i < ri->reqRingNumPages; i++) {

        m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;

    }

    for (i = 0; i < ri->cmpRingNumPages; i++) {

        m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;

    }

    RS_SET_FIELD(m, reqProdIdx, 0);

    RS_SET_FIELD(m, reqConsIdx, 0);

    RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);

    RS_SET_FIELD(m, cmpProdIdx, 0);

    RS_SET_FIELD(m, cmpConsIdx, 0);

    RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);

    trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);

    /* Flush ring state page changes */

    smp_wmb();

    return 0;

}


static bool check_overlapping_aiocb(BDRVSheepdogState *s, SheepdogAIOCB *aiocb)

{

    SheepdogAIOCB *cb;

    QLIST_FOREACH(cb, &s->inflight_aiocb_head, aiocb_siblings) {

        if (AIOCBOverlapping(aiocb, cb)) {

            return true;

        }

    }

    QLIST_INSERT_HEAD(&s->inflight_aiocb_head, aiocb, aiocb_siblings);

    return false;

}


static void qio_channel_websock_finalize(Object *obj)

{

    QIOChannelWebsock *ioc = QIO_CHANNEL_WEBSOCK(obj);

    buffer_free(&ioc->encinput);

    buffer_free(&ioc->encoutput);

    buffer_free(&ioc->rawinput);

    buffer_free(&ioc->rawoutput);

    object_unref(OBJECT(ioc->master));

    if (ioc->io_tag) {

        g_source_remove(ioc->io_tag);

    }

    if (ioc->io_err) {

        error_free(ioc->io_err);

    }

}


static av_cold int vaapi_encode_h265_init_internal(AVCodecContext *avctx)

{

    static const VAConfigAttrib default_config_attributes[] = {

        { .type  = VAConfigAttribRTFormat,

          .value = VA_RT_FORMAT_YUV420 },

        { .type  = VAConfigAttribEncPackedHeaders,

          .value = (VA_ENC_PACKED_HEADER_SEQUENCE |

                    VA_ENC_PACKED_HEADER_SLICE) },

    };

    VAAPIEncodeContext      *ctx = avctx->priv_data;

    VAAPIEncodeH265Context *priv = ctx->priv_data;

    int i, err;

    switch (avctx->profile) {

    case FF_PROFILE_HEVC_MAIN:

    case FF_PROFILE_UNKNOWN:

        ctx->va_profile = VAProfileHEVCMain;

        break;

    case FF_PROFILE_HEVC_MAIN_10:

        av_log(avctx, AV_LOG_ERROR, "H.265 main 10-bit profile "

               "is not supported.\n");

        return AVERROR_PATCHWELCOME;

    default:

        av_log(avctx, AV_LOG_ERROR, "Unknown H.265 profile %d.\n",

               avctx->profile);

        return AVERROR(EINVAL);

    }

    ctx->va_entrypoint = VAEntrypointEncSlice;

    ctx->input_width    = avctx->width;

    ctx->input_height   = avctx->height;

    ctx->aligned_width  = FFALIGN(ctx->input_width,  16);

    ctx->aligned_height = FFALIGN(ctx->input_height, 16);

    priv->ctu_width     = FFALIGN(ctx->aligned_width,  32) / 32;

    priv->ctu_height    = FFALIGN(ctx->aligned_height, 32) / 32;

    av_log(avctx, AV_LOG_VERBOSE, "Input %ux%u -> Aligned %ux%u -> CTU %ux%u.\n",

           ctx->input_width, ctx->input_height, ctx->aligned_width,

           ctx->aligned_height, priv->ctu_width, priv->ctu_height);

    for (i = 0; i < FF_ARRAY_ELEMS(default_config_attributes); i++) {

        ctx->config_attributes[ctx->nb_config_attributes++] =

            default_config_attributes[i];

    }

    if (avctx->bit_rate > 0) {

        ctx->va_rc_mode = VA_RC_CBR;

        err = vaapi_encode_h265_init_constant_bitrate(avctx);

    } else {

        ctx->va_rc_mode = VA_RC_CQP;

        err = vaapi_encode_h265_init_fixed_qp(avctx);

    }

    if (err < 0)

        return err;

    ctx->config_attributes[ctx->nb_config_attributes++] = (VAConfigAttrib) {

        .type  = VAConfigAttribRateControl,

        .value = ctx->va_rc_mode,

    };

    ctx->nb_recon_frames = 20;

    return 0;

}


void qmp_migrate_set_downtime(double value, Error **errp)

{

    value *= 1e9;

    value = MAX(0, MIN(UINT64_MAX, value));

    max_downtime = (uint64_t)value;

}


static void qemu_cpu_kick_thread(CPUState *env)

{

#ifndef _WIN32

    int err;

    err = pthread_kill(env->thread->thread, SIG_IPI);

    if (err) {

        fprintf(stderr, "qemu:%s: %s", __func__, strerror(err));

        exit(1);

    }

#else /* _WIN32 */

    if (!qemu_cpu_is_self(env)) {

        SuspendThread(env->thread->thread);

        cpu_signal(0);

        ResumeThread(env->thread->thread);

    }

#endif

}


void  helper_evaluate_flags_alu_4(void)

{

	uint32_t src;

	uint32_t dst;

	uint32_t res;

	uint32_t flags = 0;

	src = env->cc_src;

	dst = env->cc_dest;

	/* Reconstruct the result.  */

	switch (env->cc_op)

	{

		case CC_OP_SUB:

			res = dst - src;

			break;

		case CC_OP_ADD:

			res = dst + src;

			break;

		default:

			res = env->cc_result;

			break;

	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)

		src = ~src;

	if ((res & 0x80000000L) != 0L)

	{

		flags |= N_FLAG;

		if (((src & 0x80000000L) == 0L)

		    && ((dst & 0x80000000L) == 0L))

		{

			flags |= V_FLAG;

		}

		else if (((src & 0x80000000L) != 0L) &&

			 ((dst & 0x80000000L) != 0L))

		{

			flags |= C_FLAG;

		}

	}

	else

	{

		if (res == 0L)

			flags |= Z_FLAG;

		if (((src & 0x80000000L) != 0L)

		    && ((dst & 0x80000000L) != 0L))

			flags |= V_FLAG;

		if ((dst & 0x80000000L) != 0L

		    || (src & 0x80000000L) != 0L)

			flags |= C_FLAG;

	}

	if (env->cc_op == CC_OP_SUB

	    || env->cc_op == CC_OP_CMP) {

		flags ^= C_FLAG;

	}

	evaluate_flags_writeback(flags);

}


static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)

{

    DBDMA_io *io = opaque;

    MACIOIDEState *m = io->opaque;

    IDEState *s = idebus_active_if(&m->bus);

    int unaligned;

    if (ret < 0) {

        m->aiocb = NULL;

        qemu_sglist_destroy(&s->sg);

        ide_atapi_io_error(s, ret);

        io->remainder_len = 0;

        goto done;

    }

    if (!m->dma_active) {

        MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",

                      s->nsector, io->len, s->status);

        /* data not ready yet, wait for the channel to get restarted */

        io->processing = false;

        return;

    }

    MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);

    if (s->io_buffer_size > 0) {

        m->aiocb = NULL;

        qemu_sglist_destroy(&s->sg);

        s->packet_transfer_size -= s->io_buffer_size;

        s->io_buffer_index += s->io_buffer_size;

        s->lba += s->io_buffer_index >> 11;

        s->io_buffer_index &= 0x7ff;

    }

    s->io_buffer_size = MIN(io->len, s->packet_transfer_size);

    MACIO_DPRINTF("remainder: %d io->len: %d size: %d\n", io->remainder_len,

                  io->len, s->packet_transfer_size);

    if (io->remainder_len && io->len) {

        /* guest wants the rest of its previous transfer */

        int remainder_len = MIN(io->remainder_len, io->len);

        MACIO_DPRINTF("copying remainder %d bytes\n", remainder_len);

        cpu_physical_memory_write(io->addr, io->remainder + 0x200 -

                                  remainder_len, remainder_len);

        io->addr += remainder_len;

        io->len -= remainder_len;

        s->io_buffer_size = remainder_len;

        io->remainder_len -= remainder_len;

        /* treat remainder as individual transfer, start again */

        qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,

                         &address_space_memory);

        pmac_ide_atapi_transfer_cb(opaque, 0);

        return;

    }

    if (!s->packet_transfer_size) {

        MACIO_DPRINTF("end of transfer\n");

        ide_atapi_cmd_ok(s);

        m->dma_active = false;

    }

    if (io->len == 0) {

        MACIO_DPRINTF("end of DMA\n");

        goto done;

    }

    /* launch next transfer */

    /* handle unaligned accesses first, get them over with and only do the

       remaining bulk transfer using our async DMA helpers */

    unaligned = io->len & 0x1ff;

    if (unaligned) {

        int sector_num = (s->lba << 2) + (s->io_buffer_index >> 9);

        int nsector = io->len >> 9;

        MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",

                      unaligned, io->addr + io->len - unaligned);

        bdrv_read(s->bs, sector_num + nsector, io->remainder, 1);

        cpu_physical_memory_write(io->addr + io->len - unaligned,

                                  io->remainder, unaligned);

        io->len -= unaligned;

    }

    MACIO_DPRINTF("io->len = %#x\n", io->len);

    qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,

                     &address_space_memory);

    qemu_sglist_add(&s->sg, io->addr, io->len);

    io->addr += s->io_buffer_size;

    io->remainder_len = MIN(s->packet_transfer_size - s->io_buffer_size,

                            (0x200 - unaligned) & 0x1ff);

    MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);

    /* We would read no data from the block layer, thus not get a callback.

       Just fake completion manually. */

    if (!io->len) {

        pmac_ide_atapi_transfer_cb(opaque, 0);

        return;

    }

    io->len = 0;

    MACIO_DPRINTF("sector_num=%d size=%d, cmd_cmd=%d\n",

                  (s->lba << 2) + (s->io_buffer_index >> 9),

                  s->packet_transfer_size, s->dma_cmd);

    m->aiocb = dma_bdrv_read(s->bs, &s->sg,

                             (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),

                             pmac_ide_atapi_transfer_cb, io);

    return;

done:

    MACIO_DPRINTF("done DMA\n");

    block_acct_done(bdrv_get_stats(s->bs), &s->acct);

    io->dma_end(opaque);

}


static void pit_reset(void *opaque)

{

    PITState *pit = opaque;

    PITChannelState *s;

    int i;

    for(i = 0;i < 3; i++) {

        s = &pit->channels[i];

        s->mode = 3;

        s->gate = (i != 2);

        pit_load_count(s, 0);

    }

}


static void vmsvga_init(struct vmsvga_state_s *s,

                        MemoryRegion *address_space, MemoryRegion *io)

{

    s->scratch_size = SVGA_SCRATCH_SIZE;

    s->scratch = g_malloc(s->scratch_size * 4);

    s->vga.con = graphic_console_init(vmsvga_update_display,

                                      vmsvga_invalidate_display,

                                      vmsvga_screen_dump,

                                      vmsvga_text_update, s);

    s->fifo_size = SVGA_FIFO_SIZE;

    memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);

    vmstate_register_ram_global(&s->fifo_ram);

    s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);

    vga_common_init(&s->vga);

    vga_init(&s->vga, address_space, io, true);

    vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);

    s->new_depth = 32;

}


static int local_set_mapped_file_attr(FsContext *ctx,

                                      const char *path, FsCred *credp)

{

    FILE *fp;

    int ret = 0;

    char buf[ATTR_MAX];

    char attr_path[PATH_MAX];

    int uid = -1, gid = -1, mode = -1, rdev = -1;

    fp = local_fopen(local_mapped_attr_path(ctx, path, attr_path), "r");

    if (!fp) {

        goto create_map_file;

    }

    memset(buf, 0, ATTR_MAX);

    while (fgets(buf, ATTR_MAX, fp)) {

        if (!strncmp(buf, "virtfs.uid", 10)) {

            uid = atoi(buf+11);

        } else if (!strncmp(buf, "virtfs.gid", 10)) {

            gid = atoi(buf+11);

        } else if (!strncmp(buf, "virtfs.mode", 11)) {

            mode = atoi(buf+12);

        } else if (!strncmp(buf, "virtfs.rdev", 11)) {

            rdev = atoi(buf+12);

        }

        memset(buf, 0, ATTR_MAX);

    }

    fclose(fp);

    goto update_map_file;

create_map_file:

    ret = local_create_mapped_attr_dir(ctx, path);

    if (ret < 0) {

        goto err_out;

    }

update_map_file:

    fp = local_fopen(attr_path, "w");

    if (!fp) {

        ret = -1;

        goto err_out;

    }

    if (credp->fc_uid != -1) {

        uid = credp->fc_uid;

    }

    if (credp->fc_gid != -1) {

        gid = credp->fc_gid;

    }

    if (credp->fc_mode != -1) {

        mode = credp->fc_mode;

    }

    if (credp->fc_rdev != -1) {

        rdev = credp->fc_rdev;

    }

    if (uid != -1) {

        fprintf(fp, "virtfs.uid=%d\n", uid);

    }

    if (gid != -1) {

        fprintf(fp, "virtfs.gid=%d\n", gid);

    }

    if (mode != -1) {

        fprintf(fp, "virtfs.mode=%d\n", mode);

    }

    if (rdev != -1) {

        fprintf(fp, "virtfs.rdev=%d\n", rdev);

    }

    fclose(fp);

err_out:

    return ret;

}


static int64_t qemu_next_alarm_deadline(void)

{

    int64_t delta;

    int64_t rtdelta;

    if (!use_icount && vm_clock->active_timers) {

        delta = vm_clock->active_timers->expire_time -

                     qemu_get_clock_ns(vm_clock);

    } else {

        delta = INT32_MAX;

    }

    if (host_clock->active_timers) {

        int64_t hdelta = host_clock->active_timers->expire_time -

                 qemu_get_clock_ns(host_clock);

        if (hdelta < delta) {

            delta = hdelta;

        }

    }

    if (rt_clock->active_timers) {

        rtdelta = (rt_clock->active_timers->expire_time -

                 qemu_get_clock_ns(rt_clock));

        if (rtdelta < delta) {

            delta = rtdelta;

        }

    }

    return delta;

}


static int decode_motion_vector (bit_buffer_t *bitbuf, svq1_pmv_t *mv, svq1_pmv_t **pmv) {

  uint32_t    bit_cache;

  vlc_code_t *vlc;

  int	      diff, sign;

  int	      i;

  for (i=0; i < 2; i++) {

    /* get motion code */

    bit_cache = get_bit_cache (bitbuf);

    if (!(bit_cache & 0xFFE00000))

      return -1;	/* invalid vlc code */

    if (bit_cache & 0x80000000) {

      diff = 0;

      /* flush bit */

      skip_bits(bitbuf,1);

    } else {

      if (bit_cache >= 0x06000000) {

        vlc = &motion_table_0[(bit_cache >> (32 - 7)) - 3];

      } else {

        vlc = &motion_table_1[(bit_cache >> (32 - 12)) - 2];

      }

      /* decode motion vector differential */

      sign = (int) (bit_cache << (vlc->length - 1)) >> 31;

      diff = (vlc->value ^ sign) - sign;

      /* flush bits */

      skip_bits(bitbuf,vlc->length);

    }

    /* add median of motion vector predictors and clip result */

    if (i == 1)

      mv->y = ((diff + MEDIAN(pmv[0]->y, pmv[1]->y, pmv[2]->y)) << 26) >> 26;

    else

      mv->x = ((diff + MEDIAN(pmv[0]->x, pmv[1]->x, pmv[2]->x)) << 26) >> 26;

  }

  return 0;

}


static void drive_backup_prepare(BlkActionState *common, Error **errp)

{

    DriveBackupState *state = DO_UPCAST(DriveBackupState, common, common);

    BlockBackend *blk;

    DriveBackup *backup;

    Error *local_err = NULL;

    assert(common->action->type == TRANSACTION_ACTION_KIND_DRIVE_BACKUP);

    backup = common->action->u.drive_backup.data;

    blk = blk_by_name(backup->device);

    if (!blk) {

        error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND,

                  "Device '%s' not found", backup->device);

        return;

    }

    if (!blk_is_available(blk)) {

        error_setg(errp, QERR_DEVICE_HAS_NO_MEDIUM, backup->device);

        return;

    }

    /* AioContext is released in .clean() */

    state->aio_context = blk_get_aio_context(blk);

    aio_context_acquire(state->aio_context);

    bdrv_drained_begin(blk_bs(blk));

    state->bs = blk_bs(blk);

    do_drive_backup(backup->has_job_id ? backup->job_id : NULL,

                    backup->device, backup->target,

                    backup->has_format, backup->format,

                    backup->sync,

                    backup->has_mode, backup->mode,

                    backup->has_speed, backup->speed,

                    backup->has_bitmap, backup->bitmap,

                    backup->has_on_source_error, backup->on_source_error,

                    backup->has_on_target_error, backup->on_target_error,

                    common->block_job_txn, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }

    state->job = state->bs->job;

}


void ssi_register_slave(SSISlaveInfo *info)

{

    assert(info->qdev.size >= sizeof(SSISlave));

    info->qdev.init = ssi_slave_init;

    info->qdev.bus_type = BUS_TYPE_SSI;

    qdev_register(&info->qdev);

}


uint64_t bdrv_dirty_bitmap_serialization_align(const BdrvDirtyBitmap *bitmap)

{

    return hbitmap_serialization_align(bitmap->bitmap);

}


static void parse_drive(DeviceState *dev, const char *str, void **ptr,

                        const char *propname, Error **errp)

{

    BlockBackend *blk;

    blk = blk_by_name(str);

    if (!blk) {

        error_setg(errp, "Property '%s.%s' can't find value '%s'",

                   object_get_typename(OBJECT(dev)), propname, str);

        return;

    }

    if (blk_attach_dev(blk, dev) < 0) {

        DriveInfo *dinfo = blk_legacy_dinfo(blk);

        if (dinfo->type != IF_NONE) {

            error_setg(errp, "Drive '%s' is already in use because "

                       "it has been automatically connected to another "

                       "device (did you need 'if=none' in the drive options?)",

                       str);

        } else {

            error_setg(errp, "Drive '%s' is already in use by another device",

                       str);

        }

        return;

    }

    *ptr = blk;

}